EE Product News

SigmaRAM SRAMs Tap 0.13-µm CMOS Process To Pack 18 Mb In 209-Ball BGA Chip

A trio of high-speed SigmaRAM SRAMs are being made using a 0.13-µm CMOS process that have a capacity of 18 Mb and low power consumption. The three SRAMs are known as: Double Late Write and Pipelined Read/No Bus Turnaround (Sigma 1x1Dp); Late Write and Pipelined Read (Sigma 1x1Dp, Sigma 1x1Lp); and Late Write and Flow-Through Read (Sigma 1x1Lf). Each device targets different applications. The Sigma 1x1Dp is well suited for high-end switches, routers and aggregators. The Sigma 1x1Lp is an external cache solution for embedded processors requiring high density and high bandwidth buffering with a Late Write and Pipelined Read protocol. The Sigma 1x1Lf is designed for high-performance test equipment.The 18-Mb SigmaRAM SRAMs feature 1.8V operation and a 1.8V and 1.5V I/O LVCMOS interface. Maximum standby currents are less than 100 mA and 75 mA, respectively. The devices come in a 209-ball BGA package with a 14 x 22 mm footprint and 1.0-mm ball pitch. Samples are available now in 250-MHz single data rate (SDR), with x72-bit and x36-bit I/O configurations. Sample pricing is $100 each. INTEGRATED SILICON SOLUTION INC, Santa Clara, CA. (408)-588-0800.


Product URL: Click here for more information

TAGS: Digital ICs
Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.