Electronic Design

Cadence, Mentor Make Open Verification Methodology Available

The Open Verification Methodology (OVM) co-developed by Cadence Design Systems and Mentor Graphics is now available for free download from www.ovmworld.org OVM, which was recently awarded a "2007 BEST" award for EDA technology from Electronic Design, will be distributed under the standard open-source Apache 2.0 license. Its source code, documentation, and use examples are available on the website. Based on the IEEE 1800(TM)-2005 SystemVerilog standard, the OVM is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and an accompanying library that enables users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces, according to a release from Cadence. "We believe OVM will definitely accelerate the move to SystemVerilog and provide significant competitive advantage to design and verification teams around the world," Robert Hum, vice president and general manager of Mentor's design, verification and test business unit, said in a statement.

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