Power-supply sequencing is an important aspect to consider when designing with a field programmable gate array (FPGA). Typically, FPGA vendors specify power-sequencing requirements because an FPGA can require anywhere from three to over ten rails.
By following the recommended power sequence, excessive current draw during startup can be avoided, which in turn prevents damage to devices. Sequencing the power supplies in a system can be accomplished in several ways.
This article elaborates on sequencing solutions that can be implemented based on the level of sophistication needed by a system.
Sequencing solutions addressed in this article are:
- Cascading PGOOD pin into enable pin
- Sequencing using a reset IC
- Analog up/down sequencers
- Digital system health monitors with PMBus interface
Method 1: Cascading PGOOD pin into enable pin
A basic, cost-effective way to implement sequencing is to cascade the power good (PG) pin of one power supply into the enable (EN) pin of the next sequential supply (Figure 1). The second supply begins to turn on when the PG threshold is met, usually when the supply is at 90% of its final value. This method offers a low-cost approach, but...