Electronic Design

Bringing Silicon Contours Into The Designer's World

In a fashion that defies logic, “design” for manufacturing actually got its start in the manufacturing realm. Several years and silicon generations ago, semiconductor manufacturing engineers figured out that the drawn ideal shapes in a designer’s layout have sharp, crisp edges and those structures are going to change into rounded shapes (contours) when printed on silicon (see the figure).

In response, the EDA industry devised tools and technologies to take that drawn GDSII data and “munge” it to make it manufacturable. Technologies such as resolution-enhancement techniques (RET) and optical proximity correction (OPC) have gotten us by with little or no impact on electrical characteristics like timing, noise, or power. Such was the beginnings of what has come to be known as “design for manufacturing,” or DFM.

Well, that was fine for fabrication processes down to 130 nm. But starting at 90 nm, the differences between the drawn ideal shapes and real-world silicon contours became so vast that they caused catastrophic parametric failures. The puzzled designers thought, “Hmm, my design is DRC-clean and timing-clean, but yet, I have a chip failure on my hands that the manufacturer thinks is my problem! What gives?”

The issue can be summarized in this way: Up until 130 nm, the relationship between the drawn shapes and the printed shapes can be characterized as “what you see is what you get.” But at 90 nm and below, that relationship becomes “what you see is ‘not’ what you get.” In your layout editor, you see sharp, well-defined geometric shapes forming devices and interconnects. But these shapes don’t look anything like the ones that will actually be printed on silicon, shapes that possibly lead to catastrophic failures (shorts and opens).

The manufacturing process can bring significant variability in the electrical behavior of your circuit, leading to timing, noise, or power failure. These variations are highly sensitive to patterns and context around the patterns; hence, they may bring additional uncertainty into your design. So, you need to see what you’re going to get, and you need to see that in real time to make intelligent decisions about your design.

How does one solve this dilemma? What about adding lots of margin to your design? If you design your 65-nm chip with 90- or 130-nm design rules, most of your chips may be okay. But approaching the problem in this fashion is like using a rotary-dial phone instead of a touchtone phone.

To get your money’s worth from your process, you must be able to combine your GDSII with deep knowledge of the manufacturing process, including RET and OPC, and lithographic simulation to predict silicon contours. Based on these contours at various process corners, you can now analyze your design for catastrophic failures (hot spots).

Then, take these contours into extraction and analysis to compute the variation in electrical parameters, such as timing, noise, and power. Now you’re back to seeing what you will get. Only then can you make the necessary corrections in your design, long before tapeout, without waiting for days or weeks to go through the entire mask-making process. And that’s what “design” for manufacturability is all about.

See Associated Figure

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