DESIGN VIEW is the summary of the complete DESIGN SOLUTION contributed article, which begins on Page 2.
To implement custom digital logic for system-level prototyping and qualification, OEM system designers have switched from costlier FPGAs to ASICs. However, the only ASIC option was a cell-based version. Recently, though, structured ASICs arrived as an alternative. The combination of nearly cell-based density, speed, and power consumption, coupled with low nonrecurring engineering costs, short turnaround time, and compatibility, along with existing low-cost design tools, have made structured ASICs the logical choice for applications not demanding bleeding-edge performance.
The structured ASIC architecture is based on predesigned functional blocks (logic functions, timing generators, memory, and I/O) embedded in a structured manner within the base array. The ASIC's core area consists primarily of macro blocks for implementing logic functions and a fixed amount of memory blocks. The memory blocks may be integrated in the functional macro blocks and distributed throughout the array. Or, they may be embedded separately as larger blocks in the array's core. The core may also contain specialized embedded blocks, such as timing generators.
The article discusses the issues involved in deciding between a structured versus a cell-based ASIC solution. Among the topics addressed are the investments required in terms of engineering time, CAD tools, NRE cost, and schedule.
For example, for structured ASICs, the typical turnaround time from design sign-off to prototypes is one to two weeks. The cell-based version is typically eight to 10 weeks.
It's concluded that designers have a host of advantages to consider when going to structured ASICs. Ultimately, they've opened many possibilities to improve upon current synthesis flows and techniques.
|Structured Vs. Gate Array||Gate arrays use prediffused transistors to address manufacturing cycle time. With structured ASICs, the focus is on the design-cycle time and reducing the overall time from design concept to receiving parts.|
|Sea-Of-Macros||At the heart of a structured ASIC is a "sea-of-macros" architecture that implements the custom logic for each specific design. One macro, or a group of macros, can be used to implement logic functions throughout a structured ASIC.|
|Mapping Is Key||The ability to map all of the FPGA's technical aspects to the ASIC is another factor that OEM system designers must consider when contemplating alternatives for FPGA migration. Structured devices include drop-in replacements for the majority of an FPGA's special functions. A cell-based ASIC, on the other hand, may require that the designer redefine the ASIC architecture.|
|DFT Helps Save||Added savings in schedule, engineering support, and cost can be realized during the design-for-test (DFT) phase of the design flow. Structured ASIC products are typically developed with an architecture that encompasses predesigned DFT functions.|
Full article begins on Page 2
Over the last decade, most OEM system designers used FPGAs to implement custom digital logic for system-level prototyping and qualification. Unable to meet production-cost targets with the FPGA, these same OEM designers turned to ASICs for reducing cost during production implementation. Until recently, the ASIC options were limited to cell-based ASIC solutions.
Lately, a new breed of structured ASICs have been introduced as an alternative to cell-based ASICs. The combination of nearly cell-based density, speed, and power consumption, coupled with low NRE costs, short turnaround time, and compatibility, along with existing low-cost design tools, have made structured ASICs the logical choice for applications not demanding bleeding-edge performance. These structured array products are expected to play a major role in the ASIC market in the coming months and years.
The structured ASIC architecture is based on predesigned functional blocks (logic functions, timing generators, memory, and I/O) embedded in a structured manner within the base array. The ASIC’s core area consists primarily of macro blocks for implementing logic functions, and a fixed amount of memory blocks. The memory blocks may be integrated in the functional macro blocks and distributed throughout the array. Or, they may be embedded separately as larger blocks in the array’s core. The core area could also contain specialized embedded blocks, such as timing generators used to optimize the performance and perform frequency-synthesis operations of individual designs implemented with the structured array. Most of today’s structured architectures are flexible enough to further embed additional and more-complex IP blocks, such as a microprocessor core.
Structured Versus Gate Array
Despite its prediffused elements, structured ASICs differ from previous gate-array devices. Gate arrays use prediffused transistors to address manufacturing cycle time. With structured ASICs, the focus is on the design-cycle time and reducing the overall time from design concept to receiving parts. This is why structured ASIC products typically contain built-in test and predesigned power grids. These may not save much in terms of manufacturing cycle time. However, by predesigning them into the silicon fabric, the logic designer doesn’t have to spend the time or buy the tools needed to perform complex test insertion or signal-integrity checks. A structured ASIC presents a "correct-by-construction" approach that directly addresses design-cycle time as well as manufacturing-cycle time—a major enhancement over gate-array products.
Figure 1a depicts one example of a structured ASIC architecture—the AMI Semiconductor XPressArray. In this architecture, the timing generator DLL and PLL functions are predesigned and embedded in the array near the I/O ring. Each of the eight I/O banks in the pad ring is predesigned to accommodate one of several power-supply voltages. The flexible pad architecture also allows each I/O buffer within an I/O bank to be programmed to any one of a spectrum of available I/O standards.
Another important aspect is that the design-for-test (DFT) functions are predesigned and embedded in the device. In addition, the DFT functions in today’s structured arrays are compatible with industry-standard CAD tools. Compared to a cell-based ASIC, this feature reduces development time and NRE cost. In the case of the XPressArray, the DFT functions are predesigned with flexibility by including the DFT scan multiplexer in the macro cell. At the same time, the layout tool can route the connections between the multiplexer and the flip-flop as required for each specific design. This flexibility optimizes the design flow and provides adaptability for designs requiring multiple clock domains—without consuming power for unused flip-flops.
An additional feature is that performance-critical aspects of the physical design, such as clock distribution and power busing, are often predefined. These aspects of a cell-based ASIC design consume much more valuable engineering time, cost, and segments of a development schedule. For example, floorplanning of a structured ASIC is predefined by the fixed placement of the architecture. The floorplanning phase of a cell-based ASIC design can require weeks to months of valuable development schedule, requiring several iterations through the floorplanning process and static-timing analysis.
At the heart of a structured ASIC is a "sea-of-macros" architecture that implements the custom logic for each specific design. Figure 1b details the configuration of a single macro from the XPressArray that’s replicated throughout the sea-of-macros architecture. One macro, or a group of macros, can be used to implement logic functions throughout a structured ASIC. Figure 1c demonstrates how the predesigned macro functions and OEM custom designs are implemented with metallization.
Another feature is the availability of embedded memory blocks within the core of the architecture. These memory blocks may be distributed throughout the core as part of the macro block design. Or, they may be embedded as separate blocks within the core architecture.
In the case of the device depicted in Figures 1a and 1b, the memory is predesigned and integrated within the macros in the array’s core. Each macro includes 8 bits of memory designed to create 512-bit memory blocks by grouping multiple macros together. Each memory block can be configured during the design process as 512 by 1, 256 by 2, 128 by 4, 64 by 8, or 32 by 16 bits. As with the functional library, the availability of predesigned memory libraries allows for an automated path from system RTL definition to ASIC.
When deciding between a structured and a cell-based ASIC solution, many factors must be weighed. Key considerations in this decision process are the investments required in terms of engineering time, CAD tools, NRE cost, and schedule. Figure 2 shows the typical schedule for developing alternative FPGA, structured, and cell-based ASIC solutions for custom logic. Although these schedules are well understood within the industry, they don’t always reflect the overall schedule considerations faced by OEM system designers when selecting the best solution.
OEM system designers typically develop prototype systems with FPGAs for their custom logic requirements. As such, the OEM development team must first consider the compatibility between the FPGA architecture and the alternative architectures of structured and cell-based ASICs before converting the FPGA to an ASIC. In most cases, designers will find that structured ASICs provide an architecture that’s most compatible with the original FPGA design. Such compatibility will facilitate a much more direct mapping of the FPGA design to a structured ASIC. The result is a faster design process, reduced risk, and lower cost for their ASIC solution.
Because the architecture is comparable to the original FPGA design, OEM system designers can migrate to a structured ASIC using the same RTL code that they developed for the FPGA. Industry-standard tools like Synplify PRO can be used to design and develop RTL code targeting the FPGA solution. The FPGA RTL code can then be re-targeted to a structured ASIC with tools such as Synplify ASIC. The XPressArray makes this process especially straightforward because it supports drop-in replacement hardware features. This seamless migration from FPGA to structured ASIC will reduce the development cycle by four weeks for a typical design.
Mapping Is Key
The ability to map all of the FPGA’s technical aspects to the ASIC is another factor that OEM system designers must consider when contemplating ASIC alternatives for FPGA migration. The OEM designer may have used FPGA features such as memory initialization, DLL clock-management functions, and unique I/O standards.
For the most part, the cell-based ASIC libraries available in the industry don’t support direct replacements for many of these functions. However, structured devices include drop-in replacements for most of an FPGA’s special functions. Selecting a cell-based ASIC for an FPGA migration could require that the system designer redefine the ASIC architecture to accomplish the same function. This effort may retard the arrival of system cost savings realized with an ASIC.
A real plus is that the path from system design to structured ASIC design is well automated. The providers of these ASIC products also supply predesigned functional libraries that optimize the mapping from RTL code to macro configuration. These libraries, coupled with generally available CAD tools like Synplify ASIC, let system designers focus on the system-critical aspects of the design effort: ASIC design definition and performance optimization.
One key benefit in the design path of a structured ASIC, as opposed to cell-based implementation, is how much the designer must "steer" the synthesis tool. Because structured ASICs contain both precharacterized base metallization and macro cells that are preoptimized, the synthesis flow benefits in many ways:
- Wireload models can be more accurate
- Floorplanning is made easier
- IP integration can be streamlined
- Memories can be inferred from RTL and automatically implemented, not compiled and instantiated
- Power grids can be taken into account before synthesis, not afterwards
Going one step further, the ASIC’s "structure" lets EDA vendors customize their tools to automatically consider issues like vendor-specific design-rule checking and power-grid analysis prior to customer handoff. Not only is the design flow streamlined, but it also leads to lower risk for the designer by having handoff considerations handled in the tool, not by the ASIC vendor.
The technical features of a structured ASIC provide additional engineering and schedule benefits as compared to a cell-based solution. Figure 3 summarizes the design flows for the two approaches. Significant differences exist between these two design flows that affect the required engineering support, cost, and schedule to be evaluated by OEM system designers when selecting a design approach.
DFT Helps Save
Added savings in schedule, engineering support, and cost can be realized during the DFT phase of the design flow. Structured ASIC products are typically developed with an architecture that encompasses predesigned DFT functions. For example, the XPressArray product includes a DFT scan multiplexer in each individual macro with a flip-flop. This significantly reduces the engineering effort required to manage DFT timing issues in the timing-closure loop. With a cell-based ASIC, the flip-flops and DFT functions are separate cells. Because the physical routing interconnect between these cells varies from flip-flop to flip-flop, cell-based ASICs typically have a greater number of DFT timing issues. This ultimately requires more engineering effort to resolve.
Designers of structured ASICs also realize significant savings in engineering time compared to a cell-based ASIC. This is accomplished by eliminating the floorplanning phase of the design process.
Structured architectures are predesigned with an inherent floorplan. For example, the I/O, memories, and timing generators in the XPressArray product are predesigned with a fixed placement in the architecture. Although cell-based ASICs need more flexibility in the placement of these functions, they also require many iterations of the physical design placement to resolve timing and packaging issues caused by variations in the physical design. This requires a great deal of engineering effort and schedule.
Compared to cell-based ASICs, OEM system designers also realize significant cost and schedule savings during the prototype fabrication process. For example, the typical turnaround time from design sign-off to prototypes is one to two weeks. This same effort is typically 8 to 10 weeks for a cell-based ASIC. Cost savings is achieved because the tooling cost of the array’s predesigned portion is shared across many designs, while custom tooling is required for each masking step of a cell-based ASIC. For example, the design’s specific tooling cost for a 0.18-micron XPressArray design can be as low as $30K, while the typical tooling cost for a 0.18-micron cell-based ASIC is $300K.
Designers clearly have many advantages to consider when going to a structured ASIC: NRE cost is just a fraction of a cell-based ASIC; piece-part cost is substantially less than an FPGA; and migration from FPGA-based prototypes is streamlined. Moreover, customized synthesis technology brings another advantage—performance. This may be surprising, given that the architecture inherently isn’t as high performance as a cell-based approach. But by customizing the synthesis process, much of this performance can be regained by the design tools.
Custom synthesis uses direct information about the devices to pick the best possible cells for a function, and can specifically tune datapath and arithmetic operator generation to that unique fabric. With the fixed ratio of flip-flops, inverters, multiplexers, and NANDs, custom synthesis will ensure that ratios between the various types of primitives are met, thereby improving both timing and area. Structured ASICs have opened many possibilities to improve upon current synthesis flows and techniques.