Electronic Design

EDA: Overview

Tooling Up For A Nanometer World

Dramatically shifting sands in the design world await engineers, particularly those involved with ASICs or customer-owned tooling (COT) ICs. Nanometer design is becoming reality, but its ultimate success hinges on the development of a very different design methodology. To that end, the EDA industry continues to pull together the pieces for a collective move to design at levels of abstraction higher than the register transfer level (RTL). Once it does, be prepared to rethink your approach to design if you haven't already done so. The wall between design and implementation, once firmly anchored at the gate-level netlist, will be torn down and rebuilt elsewhere. At nanometer geometries, that gate-level netlist just doesn't carry enough information when the design is physically implemented to make it feasible.

It's not as if there aren't significant technical, cultural, and economic obstacles impeding the path toward achieving a fully workable nanometer design methodology. Nevertheless, we can look to 2003 as a year in which EDA strives to pull designers into new methodologies that account for physical effects.

If you're about to embark upon a next-generation COT or ASIC design, you must determine where to start. Emerging system-level design approaches come into play here. Although there hasn't exactly been a stampede to design at higher levels of abstraction, interest is surging. Design at the system level can help speed architectural exploration and system partitioning. Watch for developments in a tool flow that take the results of these "what-if" explorations down to a concrete level of abstraction. Behavioral synthesis may not have been the answer; others could emerge.

SystemC seems to be the frontrunner among the crop of system-level design languages. Still to be resolved, though, is the fundamental disconnection between hardware and software design at the algorithmic level. Hardware designers remain wary of C-level design and perhaps rightfully so, given the lack of a tool flow that takes them to implementation.

If we can't have a means to move from algorithmic expressions of design directly into at least an RTL description, perhaps an interim step can help solve the dilemma posed by nanometer design. At geometries of 100 nm and below, timing closure hinges on delay calculations. Gate delays don't dominate these calculations, however, but rather interconnect delays. Therefore, it's imperative that designers have a view into the physical realities implied by their design at any and all levels of abstraction.

Virtual prototyping best exemplifies that view. In the nanometer age, IC design must become a process of successive approximation. Virtual prototyping gives designers a running start in that direction. Even at high levels of abstraction, the availability of a virtual prototype provides a basis in reality to which layers of deepening physical detail can be added throughout the design process. With more physical detail comes a design representation that nudges closer and closer to the real thing. The ever-present fudge factor inherent in modeling thus shrinks and predictions of parasitics and gate-level timing become more accurate. Before long, we're looking at a handoff point that falls higher in the process than a gate-level netlist.

Even if there's a shift of design handoff to a higher abstraction level, nanometer design still brings a host of verification challenges. As design methodologies strain to accomplish more at higher levels of abstraction, design analyses and verification remain mired at the transistor level. Moreover, static timing analysis techniques, employed at the gate level, can open designers to some nasty surprises when their results are compared with transistor-level dynamic simulation.

Further complicating matters is the increasing analog and mixed-signal (A/M-S) content in system-on-chip (SoC) designs. Today, 25% of SoC designs are A/M-S. In five years that figure will balloon to 75%. Design and integration of those analog blocks will take up 40% to 50% of overall design time. Mixed-signal verification must evolve to embrace the simultaneous modeling of digital circuits at high levels of abstraction and A/M-S portions at the transistor level to improve efficiency.

By and large, trends in IC design propagate upward to system level as those systems increase in complexity. In fact, the need to consider physical implementation is already being felt at the system level. Circuit designers find themselves having a hand in board layout, setting up rules for layout designers, and generally immersing themselves in prelayout signal integrity analysis. New generations of pc-board tools are accounting for these issues, offering time- and frequency-domain analysis.

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