Electronic Design

EDA Remains The Enabler Of Much-Needed Innovation

A host of emerging tools and methodologies helps you retain your design edge in a time when differentiation means everything.

Some years ago, the Electronic Design Automation Consortium (EDAC) adopted the phrase “Where Electronics Begins” as a tagline. Coined by Richard Goering during his EE Times days, the phrase remains more than apt for EDA.

As silicon integration grew more complex over the past three decades, the automation of otherwise manual and labor-intensive phases of the design cycle became ever more critical. one could scarcely imagine today’s systems-on-a-chip (SoCs) reaching tapeout without modern EDA flows behind them.

Generally overlooked and underappreciated, the EDA industry continues to create the tools and methodologies that help design engineers realize their conceptual dreams. Good thing, too, because the electronics industry can sure use another iPod or BlackBerry— something that will rev up the economic engines and help save dwindling engineering jobs. starting from the front end of the design cycle and moving toward tapeout, some of these tools and methodologies let designers forget the drudge work and concentrate on the differentiation that defines a winner.

WHERE EDA BEGINS
Design engineers are finally feeling enough pain in the architectural-definition stage to begin embracing the concept of electronic system-level (ESL) design. ESL has taken its lumps over the years as a technology that never arrived. But the truth is that an infrastructure is now in place, enabling design teams to get real value out of ESL methodologies. many adopters are taking an incremental approach to diving into ESL, picking and choosing the elements of an ESL methodology that make the most sense for them (see “Is ESL Adoption Really All That Difficult?” Electronic Design, Feb. 12, 2009, www.electronicdesign.com, ED Online 20569).

When it comes to examples of the fleshing out of an ESL infrastructure, witness the recent announcement of the Open Core Protocol-International Partnership’s (OCP-IP’s) advanced systemc transaction-level modeling (TLM) kit. Based on the open systemc initiative’s TLM 2.0 modeling standard (see “TLM-2.0 APIs Open SystemC To Mainstream Virtual Platform Adoption,” ED Online 21132), the TLM kits come free with OCP-IP membership. They should go a long way toward indoctrinating people with the benefits of transaction-level modeling. Along the way, kit users can expect to save a bundle that they would have otherwise blown on development, documentation, and training.

Because the kit comprises a standardized Open Core Protocol-based means of setting up a virtual platform (see “Virtual Platforms 101,” ED Online 21129), users needn’t puzzle out how to implement a working interface protocol between systemc block models, nor do they have to test their implementation. The end result is a fast track to a transaction-level hardware/software co-verification environment, which in turn can deliver huge time savings in system integration.

Alongside the ESL infrastructure, one must have tools to comprise a methodology. A recent entry into the vendor ranks, DOCEA Power, has chosen to pursue power and thermal analysis at the system level. All designers face the gremlin of power consumption, and it’s best to get a handle on it sooner rather than later. effective management of power consumption and thermal effects is proving to be a key differentiating element in the consumer electronics arena.

DOCEA Power’s flagship Aceplorer 1.1 allows system architects to generate power models for an SoC’s functional blocks and put them together into a system model (Fig. 1). An Aceplorer power model is a common XML-based description for capturing power behavior from informal requirements, even if the sources are heterogeneous (spreadsheet, datasheet, specification, IP-XACT description, and library). it can mix components at different levels of accuracy and model the interdependencies between parameters for more accurate and reliable power estimates.

The tool automatically generates power intent for the design according to IEEE 1801 or the Unified Power Format. As a result, users can nail down their power specification and manage power intent at any stage of the design flow. Thermal modeling in Aceplorer is based on a dynamic compact thermal model (DCTM) generated by proprietary algorithms. meanwhile, a network of thermal resistors and capacitors represents package and environmental thermal characteristics.

BUS DESIGN MADE SIMPLE
Consumers want wireless capability in almost everything today, but building that functionality into an SoC design pumps up the complexity; some baseband chips have up to 50 to 60 IP cores. more cores means a more complicated interconnect structure, which in turn means more time spent wrestling with communication protocols. As a result, architecture definition and verification are now two of the fastest-growing costs of SoC design.

As one of the driving forces behind OCP-IP, Sonics has long been in the forefront of automating the process of creating interconnect IP. The company’s latest offering, the Sonics Network for AMBA Protocol (SNAP), is intended to simplify on-chip bus design for these complex embedded SoCs by turning an entire multilayer bus structure into an IP block.

What can SNAP do for an embedded SoC designer? The primary benefits are reduced wire congestion and simplified overall bus design (Fig. 2). The bus structures created by the SNAP platform are less a traditional bus structure and more of an on-chip network. It also creates a decoupled architecture in which cores can be swapped out very cleanly at any point in the design cycle without adversely affecting the architecture itself.

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In the SNAP scheme, master AHB layers can connect up to eight cores per layer with improved arbitration. Further, AHB/APB slave branches can connect up to 16 slave cores per branch. The result is an interconnect matrix backbone that lets designers build topologies based on performance needs. For example, CPUs and memories can connect to high-speed paths with zero latency while slower peripherals can connect to peripheral branches, allowing optimization of gate counts.

A set of development tools that let designers quickly capture bus designs ties the SNAP solution together. The environment lets you evaluate key details about your proposed bus architecture in advance, including gate count, power dissipation, and speeds. The GUI enables users to enter information on the cores being connected and various interconnect parameters. The tool automatically generates the RTL for the interconnects themselves.

SPEEDING UP SPICE
On the full-custom design side, many designers have turned to fast-Spice derivatives for analog/mixed-signal simulation. Sure, they trade off a little accuracy, but they gain a great deal of speed. You can make up for the accuracy by simulating critical paths in a traditional Spice simulator in parallel. Meanwhile, for the bulk of your design, fast-Spice simulation gives you a big boost in verification speed.

Meanwhile, fast-Spice simulators keep improving in accuracy while still offering most, if not all, of the speed advantages. To wit, Berkeley Design Automation Inc. rolled out the 2009_05 release of its Analog FastSPICE (AFS) unified circuit verification platform.

Within a single executable, the AFS platform enables analog, mixed-signal, and RF design teams to verify what would otherwise require numerous simulators. Berkeley claims that this release delivers foundry-certified, true Spice accuracy with runtimes that are five to 20 times faster than traditional Spice for every type of analysis on circuits with up to 10 million elements. The result is twice the efficiency of traditional Spice simulators.

The platform includes new matrix solvers that deliver efficient convergence and fast transient analysis for pre- and post-layout circuits. In addition, the platform’s multicore capability provides up to two times more performance than singlethreaded analog fast-Spice simulators when run on up to four cores. An enhanced Monte Carlo analysis engine supports all commonly used features, including Latin hypercube sampling, in the industry’s most popular netlist styles.

GETTING IT RIGHT
There’s still significant room for innovation in the physical verification of large SoC designs, and such innovation ultimately translates into a competitive advantage for designers. It would be wonderful if physical verification runs didn’t take so long, but design teams will have to live with that downside of the process. Multicore tool architectures are chipping away at the runtimes. Still, if physical verification runtimes have to be so long, it would be nice if the runs could at least be more accurate.

That’s where Silicon Frontline Technology comes in. The startup launched its flagship tools for post-layout verification: F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices. These tools, which incorporate 3D technology, deliver guaranteed accuracy for full-chip, post-layout verification, according to Silicon Frontline. Fitting into standard design flows, the tools facilitate simpler adoption and quicker closure of the post-layout verification loop, the company says.

Silicon Frontline’s 3D parasitic-extraction technology lets users specify the level of accuracy desired, net by net, at block level or with regular expressions. The tools use an advanced field solver that eliminates the performance and capacity issues inherent in older field-solver technology, accomplishing full-chip extraction with greater accuracy, the company claims.

In Silicon Frontline’s benchmarks, F3D completed extraction of a 65-nm SoC design in under 10 hours. Extraction runs for metal-onmetal capacitors take less than three minutes versus over seven hours with standard field solvers. When performing extraction on a 40-nm design, F3D delivers accuracy that’s within 2% of silicon, Silicon Frontline says.

Pre-qualified by major foundries for accuracy, performance, and capacity, F3D suits sensitive analog and AMS circuits where coupling is a challenge—analog-to-digital converters, digitalto- analog converters, circuits with differential signals, MIM/MOMCaps (metal-insulator-metal/ metal-oxide-metal) and 3D devices, image sensors, and RF and high-speed designs—and for circuits manufactured at advanced technology nodes (65, 40, and 32 nm). R3D target applications include discrete or embedded power devices, where efficiency and reliability are important, as well as designs requiring analysis of large metal interconnects.

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