A NEW OPEN VERIFICATION LIBRARY STANDARD has been approved by Accellera's Board of Directors. The Accellera OVL Verilog/SystemVerilog Assertion technical committee also has approved the standard, Open Verification Library (OVL) 1.0. The OVL standard results in better HDL designs, thanks to pre-defined checkers written in either Verilog or SystemVerilog that enable designers to immediately take advantage of assertion-based verification. The library includes 31 assertion checkers for both Verilog and SystemVerilog. These checkers cover many of the common properties that designers check during the functional verification of RTL code. The OVL v1.0 standard is available for download at the Accellera Web site. Visit www.accellera.org for more information.
IN A COLLABORATION WITH THE CHINA ACADEMY OF SCIENCE (CAS), Mentor Graphics is building a joint laboratory of system design in Beijing. This phase of collaboration builds on an earlier agreement between the EDA Center of CAS and Mentor. The lab is intended to elevate the level of design work at CAS. Mentor also will train designers in China, providing a high-technology learning/training platform. For details, visit www.mentor.com.