Support for Openaccess v2.2 has been added to Verific's HDL parsers for Verilog, SystemVerilog, and VHDL. The Open-Access interface offers a link to the Verific parsers, offering fast netlist import, along with full RTL support to the OpenAccess 2.2 database. OpenAccess is a community effort to provide interoperability among IC design tools through an open-standard applications programming interface and reference database. Verific's parsers are a key element of a path allowing synthesized RTL to be stored in an OpenAccess database. Visit www.verific.com for more information.
Virtual prototyping of peripherals has never been easier than with VaST Systems Technology's Peripheral Device Builder. The tool enables users to quickly develop models of peripheral devices such as interrupt controllers, DMA engines, timers, clocks, and memory controllers. These models then can be used with VaST's CoMET and METeor tools to create virtual system prototypes for rapid platform verification and integration. Peripheral Device Builder will be available for general release at the end of March with a one-year, node-locked license price of $25,000. Learn more at www.vastsystems.com.