Automating the process of RTL closure, Blue Pearl Software's Indigo RTL Analysis identifies functional problems in RTL before synthesis to gate level. This reduces the number of design iterations by resolving issues such as synchronization of clock-domain-crossing data and logic race conditions (e.g., write-write, read-write, and combinational loop races). Indigo automatically pinpoints the lines of source code causing the problems. The tool's functional-analysis technology runs at chip level without synthesizing to gates. Available for Solaris, Linux, and Windows, Indigo starts at $5000. It currently supports Verilog, with SystemVerilog and VHDL support coming later in 2005. Visit www.bluepearlsoftware.com for more information.
SystemVerilog support and rule checking were added to TransEDA's VN-Cover and VN-Check verification tools. For VN-Cover, SystemVerilog support means users can exploit SystemVerilog constructs such as enumerated types, records, and user-defined types while accurately measuring code coverage. Users of VN-Check, a configurable rule checker, can now check SystemVerilog code for name and style rules very early in the design flow. The new version of VN-Check also implements numerous assertion-oriented rules. The updated versions of both tools are available now in beta versions. Learn more at www.transeda.com .