SUPPORT FOR THE LATEST SPICE MODELS has been added to Tanner EDA's T-Spice analog simulation platform. Version 11 of T-Spice now supports the latest Berkeley BSIM models up to the v4.4.0 release. These models enable users to accurately simulate MOSFET physical effects down to the sub-100-nm range. New modeling features include gate and body resistance networks for RF modeling; non-quasi-static model; comprehensive geometry-based parasitic models for multifinger devices; and stress-effect modeling. Depending on configuration, T-Spice v.11 starts at $5000 per seat for either networked or node-locked licenses. Visit www.tanner.com for more information.
A GRAPHICAL DESIGN ENTRY ENVIRONMENT for ASIC and FPGA designers provides a fast, accurate means of performing design entry, modification, and maintenance. HDL Works' EASE design-entry tool has been optimized for use with Actel's Libero IDE design flow, and it handles VHDL, Verilog, and mixed-language designs. The EASE tool gives users a choice of graphical or text-based design entry. It automatically generates optimized HDL code in either VHDL or Verilog. In addition, it supports standard version-control environments for design and configuration management. Prices for the EASE tool start at $4200. Evaluation copies can be downloaded from the HDL Works Web site at www.hdlworks.com. For details on the Libero IDE design flow, visit www.actel.com.