THOUSANDS OF ASSERTIONS WRITTEN AUTOMATICALLY is the promise of a new Verilog-language variant and an associated toolset from startup Assertive Design. Through use of the DesignPSL language, which leverages the ability of the Property Specification Language (PSL) to capture design intent, designers can automatically create error and coverage assertions--many more than one per line of code. Tools include a source analyzer, assertion generator and simulator, and more. Pricing is set at about $35,000/seat for a one-year license for the language and tools. Visit www.assertivedesign.com for more information.
AN RF/MICROWAVE DESIGN SUITE from Eagleware/Elanix has seen significant enhancement with the addition of new capabilities. Genesys 2005 includes the WhatIF frequency planning tool, which analyzes the spurious performance of intermediate frequencies (IFs). Genesys 2005 also includes the Cayenne time-domain simulator, which offers direct use of S-parameter data. For details, visit www.eagleware.com.