Electronic Design

EDA Webcast Set For Feb. 13

On Feb. 13 at 2 p.m. EST, this webcast will examine what is to be gained for low-power SoC at levels of abstraction above RTL and look at how tools and methodologies are evolving to suit optimizing for power. It will present new ESL modeling methodologies and IP ReUse concepts with which designers can efficiently build TLM SoC platforms that can accommodate accurate power assessments and substantial power optimization under real-time use cases. Sponsored by Mentor Graphics. To register, click here

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