Electronic Design

Electronic Design Automation

Design Tool Provides Accurate System Simulation In C
Afterburner 1.0 creates fast and accurate C models of RTL designs for early verification of electronic systems. It requires no change to current RTL design methodologies, so designers can still capture designs in Verilog.

Also, the tool uses synthesizable RTL to create time-accurate C simulation models, and it ensures that the RTL and C models are consistent. Its developers have tested it on processor, communications, signal processing, and peripheral designs. Patented RTL-C simulation technology allows the Afterburner C models to simulate 1.4 to 7.8 times faster than compiled Verilog models.

Designers can use Afterburner to conduct system verification in C without a simulation license, reducing the software development cost. IP suppliers can deliver Afterburner C models as protected binary files for early embedded-software development. They also can create models that provide different levels of design visibility for different types of users—internal or external. Updated C models can be quickly generated at any time in the design process, assuring consistency among the RTL and the C models used by the software developer.

Afterburner 1.0 comes with the ASVP Builder. It's available for Solaris on Unix. A floating perpetual license costs $135,000, while a monthly license costs $9900. The API is licensed for free.

CAE Plus, 910 Jollyville Rd., Ste. 200, Austin, TX 78759; (512) 338-0192; www.cae-plus.com.



Design Kit Lets Engineers Develop And Prototype MEMS Devices
The JumpStart design kit provides a turnkey method for developing and prototyping MEMS devices. It includes the Catapult MEMS design tool, which comes with integrated layout generators. It also features an engineering design kit for Cronos-certified multi-user MEMS processes (MUMPs) and a reserved slot on a MUMPs fabrication run. Developers can use this kit to create, verify, and optimize a design via the Catapult software and then seamlessly transfer the design to Cronos Integrated Microsystems Inc. for fabrication according to the specifications. In about 12 weeks, customers receive 15 prototype chips as unreleased die. Multi-user photomask generation, wafer fabrication, dicing into 1- by 1-cm individual chips, and shipping are included. Priced at $6000, JumpStart is available on Unix and Windows NT platforms. Special packaging and release options are available.

Microcosm Technologies Inc., 4001 Weston Pkwy., Ste. 200, Cary, NC 27513; (919) 854-7500; fax (919) 854-7501; www.memcad.com.



Free Tool Automates Logic Design For Embedded Systems
With PSDsoft Express, embedded-system designers no longer have to design any of the necessary logic for memory decoding, segmentation, paging, chip selects, or pin assignments required when external memory is added to the design. Used in conjunction with the manufacturer's PSD microcontroller support ICs, PSDsoft Express automatically generates all of the logic equations based on point-and-click menus in the tool. This process is transparent to the user, as well. The logic is guaranteed to be syntactically correct, while the tool prevents incorrect pin assignments and/or overlapping memory addresses. Both of these problems are fairly common when external memory is used.

Also, designers that use PSDsoft Express won't have to write any HDL at all. Instead, the tool walks them through the whole process. They simply click on the appropriate option on various menus to select and configure the microcontroller or PSD they're using to assign a function to a pin, to create an MCU system memory map capable of paging and swapping, or to generate chip selects. Furthermore, PSDsoft Express operates under Windows 95, 98, and NT operating systems.

PSDsoft Express can be downloaded for free from the company's web site.

Waferscale Integration, 47280 Kato Rd., Fremont, CA 94538; (510) 656-5400; fax (510) 657-5916; www.waferscale.com.



Software Automatically Creates Layouts For Standard Cells
The CLASSIC-SC automated layout creation tool delivers high-quality layouts while easing the deployment of software in library development projects. Designers can use it to rapidly create quality handcrafted layouts in a very short time.

Combined with sophisticated library data management utilities, this capability gives users an efficient, fast, and high-quality tool for library development. It includes new transistor placement techniques that have been implemented to allow for automatic transistor staking. Also, it features a reduction in diffusion gaps and an improved handling of highly folded transistors.

A new graphical user interface lets users enter and modify design rules, cell architectural features, and layout preferences. This release also supports multiuser library access and new library management capabilities, including a Library Browser that lets users monitor layout creation jobs, check the current run status of cells in the creation process, and view vital statistics about a library as well as individual cells. CLASSIC-SC also automates the transistor-level design of ICs and enables customers to produce handcrafted quality layouts in a fraction of the time of traditional methods.

Contact the company for pricing information.

Cadabra Design Automation, 3031 Tisch Way, Ste. 200, San Jose, CA 95128; (408) 260-2500; fax (408) 260-7100; www.cadabradesign.com.



Model Packager Solves VHDL IP Protection And Distribution Issues
The Affirma model packager for VHDL provides high-performance, protected VHDL simulation models. Based on industry-standard interfaces, it increases the accessibility and benefits of model packaging.

Models packaged with the Affirma support the IEEE 1499 Open Model Interface (OMI) and the IEEE 1364 Programming Language Interface (PLI) standards for direct connection with a wide range of simulation environments. They also use standard interfaces. Even so, they do not require a license to run. The manufacturer doesn't charge extra for the use of shared IP provided by the Affirma model packager. This tool is delivered to customers as part of the Affirma NC VHDL, NC Verilog, and NC simulator products at no extra cost.

Authors who want to generate a model that runs with any tool besides an Affirma NC simulator can purchase an Affirma model packager export license for a yearly subscription fee of $10,000. Additional packaging or royalty fees for the OMI interface aren't charged, since it is a public standard.

Cadence Design Systems, 555 River Oaks Pkwy., Bldg. 1, San Jose, CA 95134; (800) 746-6223; fax (408) 954-8917; www.cadence.com.

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