Electronic Design

If Costello Is Here, Can Abbott Be Far Behind?

The first day of exhibits at the 43rd Design Automation Conference has come and gone, and to be sure, a man who walked away from the EDA industry 10 years ago stole the show. In his Monday keynote address, Joe Costello, the one-time Cadence CEO (and now chairman and CEO of Orb Networks), reminded the EDA industry of his unique style and personal magnetism.

The address, titled “iPod Or Iridium: Which Are You Going To Be?” was a rollicking fun hour-plus of vintage Joe Costello. Speaking to a packed (and enormous) ballroom in the Moscone Center, Costello managed to meld somewhat painful stories from his own career with that of the failed Iridium satellite-phone venture to paint a picture of how not to launch and market a product. By contrasting those stories with that of Apple’s iPod, Costello left his audience with his rules of thumb for successful product launches. Along the way, he elicited quite a bit of laughter. The man does put on a pretty good show.

You had to be there to appreciate some of Costello’s rules, but it’s not unlikely that the phrase “think like a fish” will be entering the lexicon of the EDA industry’s marketing community. Basically, what Costello was relating through the time-honored medium of a “fish story” was a very old rule in marketing, but one that is all too often overlooked: know your customers and understand their needs. Costello also related his penchant for instructing his marketing people to “write the press release first.” Why? Simple: If you can’t clearly articulate what’s going to make the product you’re about to develop so special before beginning, perhaps you should reconsider the project altogether.

Another well-attended event on this opening day of exhibits was a DAC Pavilion session in which Gary Smith, Gartner Dataquest’s chief EDA analyst, unveiled his annual “What To See @ DAC” list. Not surprisingly, this year’s edition is dominated by ESL and DFM/DFY offerings.

Smith seems greatly impressed by Imperas, a startup which hasn’t even announced a product yet. Led by CEO Simon Davidmann (of Co-Design Automation/Superlog fame), Imperas intends to address the impending threat of software for multicore SoCs (see ED Online 13131 for more on that topic). Imperas will be launching tools that will aid software developers attempting to write code for what some are calling “second-generation SoCs,” or SoCs with multiple compute engines (see ED Online 12873). Bearing in mind that it hasn’t been announced, Smith termed the Imperas product “possibly the most important product at DAC this year.”

Also on Smith’s must-see list is Tenison Design Automation for its recently-launched VTRAC technology. Building on its existing technology, which automatically synthesizes C++/System C models from RTL for use in ESL environments, Tenison’s VTRAC comprises a library of industry-standard interface transactors that enable rapid integration of new and legacy IP blocks within system-level modeling environments. It connects IP in SoC models, at any abstraction level from RTL up to the transactional Programmer’s View (untimed). With the VTRAC launch, Tenison is making progress toward its goal of closing the “model gap” that has conspired to render ESL less usable than some would like.

ArchPro Design Automation, a first-time DAC exhibitor, made Smith’s cut for its RT-level power optimization products (see ED Online 12943). At DAC, ArchPro is touting success in a joint R&D project with ARM in which they were able to verify a 65-nm, multi-voltage SoC using ArchPro’s Multi-Voltage Simulator (MVSIM) tool. The SoC used ARM’s Intelligent Energy Manager technology.

There hasn’t been much in the way of EDA mergers and acquisitions of late, but Magma Design Automation made one of the bigger splashes in that pool by announcing its acquisition of ACAD Corp. and its simulation/power-analysis technologies. The first product emerging from that acquisition is Magma’s FineSim Pro full-chip circuit simulator. FineSim Pro’s claim to fame is its ability to allow full-chip transistor simulation in three different modes (turbo mode for highest speed, analog mode for higher accuracy and capacity, and Spice mode for complex mixed-signal blocks). Further, the tool can leverage distributed processing to eliminate Spice-simulation bottlenecks.

Yet another relatively new player in EDA is DAFCA, who’s at DAC showing its ClearBlue product suite for post-silicon SoC validation. Very few SoCs ever reach first silicon without some functional errors. DAFCA’s technology enables designers to incorporate a reconfigurable debug infrastructure into their chips that will facilitate observing, discovering, and diagnosing those functional errors at speed.

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