>> Transeda's VN-Property property checker and analyzer now supports Accellera's Property Specification Language (PSL, formerly known as IBM Sugar). For details, visit www.transeda.com.
> On the heels of its acquisition of LISATek, CoWare has rolled out new versions of its LISATek EDGE Processor Designer, RIM Software Designer, and HUB System Integrator tools. The tools, which automate creation and modeling of embedded processors for systems-on-a-chip, now support Co-Ware's N2C design environment. Visit www.coware.com.
>> Enhancements to Synplicity's Certify verification synthesis software bring more insight into the ASIC prototyping process, including gated-clock reporting and source-code level partitioning. Also included are a new timing engine and timing analysis capabilities. Surf to www.synplicity.com.