Electronic Design

Verification IP Evolves To Drive Efficiency

These days, system-on-a-chip (SoC) design and verification means serious challenges. The register transfer level (RTL) and testbench for the design could add up to 40 million lines of code requiring more than 150 Gbytes of memory. The design could encompass more than 10 communications protocols. Coverage data alone might be a terabyte or more. Within all that code, 300,000 assertions could be lurking, as could up to 200 power domains.

These factors add up to an enormous amount of expertise that must go into the efforts of verification engineers. Writing tests, debugging, and performing analysis for all those protocols (including the various permutations of MIPI) comprise perhaps more of a challenge than it is for the intellectual property (IP) integrators. Designs such as these strain current verification-IP (VIP) technology, which derives from the last decade’s often proprietary verification languages and methodologies, to its limits.

The verification landscape is quite different today, which calls for a new generation of VIP that reflects that landscape. With its Discovery VIP, Synopsys has taken a crack at bringing VIP into the present (see the figure). Rather than being based on those older verification languages such as E or Vera, Discovery VIP is built on a 100% SystemVerilog architecture and includes native support for the Universal Verification Methodology (UVM), the Verification Methodology Manual (VMM) for SystemVerilog, and the Open Verification Methodology (OVM).

Because Discovery VIP runs natively in all simulators, it does away with the practice of using Programming Language Interface (PLI) wrappers, which adversely affect simulation performance. The result, claims Synopsys, is performance between two and four times faster than older VIP. If you use the VIP with the UVM, you simply compile to the UVM class library.

An automatic configuration capability lists all parameters, provides legal values for each one, and makes it easier to set up parameters without having to sift through manuals to look for potential conflicts. The VIP also offers built-in test plans to help ensure that coverage is complete. A key feature is a protocol-aware debugging environment that Synopsys calls “Protocol Analyzer.”

The Discovery VIP portfolio spans from the AMBA protocols to UARTs with many more in between, including numerous MIPI variants.

Synopsys
www.synopsys.com/VIP/

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish