EE Product News

Web-Based Design Aid Eliminates NRE Charges

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Claiming to eliminate non-recurring engineering (NRE) charges and to cut months from ASIC design cycles, ClearLogic ASIC, a web-based ASIC design flow, allows designers' to map their Altera-based FPGA prototypes into the company's ASIC designer via the Internet. By submitting the bitstream for their prototypes at the company's website, sample quantities become available within two weeks and production quantities with six weeks.
A free sample can be gotten by logging onto the compahy's website and clicking on the "First Article Request" form and filling in the request form. Select the Altera device used for the prototype, attach the bitstream file and click the "Submit" button. The design is said to take less than five minutes.

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