Originally broadcast on September 28, 2023. Now available On Demand.
Sponsor: SiTime
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Summary
Precise and accurate timing is needed for a wide variety of applications such as radar, instrumentation, network synchronization, GNSS, O-RAN and 5G networks. For over 70 years, these applications relied on oven-controlled oscillators (OCXOs) to provide a stable timing reference. Historically, these oscillators have a reputation of being unreliable, difficult to design with, and susceptible to environmental stressors, often performing in unexpected ways in the field.
What you will learn in 30 minutes
- How the latest innovations in OCXOs can benefit your application and enable deployment globally with a single robust design
- How to design timing subsystems faster with fewer components, simplifying the design experience
- How to get predictable performance in real-world environments, with greater immunity to supply noise, load sensitivity, and environmental stressors
- How to lower power consumption in timing subsystems and get a wider range of support across temperature and frequency
Speakers
Gary Giust, PhD | Sr Manager, Technical Marketing | SiTime
Gary Giust, PhD, heads technical marketing at SiTime working to optimize timing at the architectural level. Prior to SiTime, Gary founded JitterLabs, and previously worked at Applied Micro, PhaseLink, Supertex, Cypress Semiconductor, and LSI Logic. Gary is a timing industry expert, has co-authored a book on timing, is an invited speaker, an internationally published author in trade and refereed journals, was a past Technical Chair for the Ethernet Alliance's backplane subcommittee, and holds 20 patents. Gary obtained a Ph.D. at Arizona State University, Tempe, an MS at the University of Colorado Boulder, and a BS at the University of New Hampshire, Durham, all in electrical engineering.
Jagdeep Bal | Director, Customer Engineering | SiTime
Jagdeep Bal is a member of the Customer Engineering team at SiTime. He focuses on helping customers find solutions to their system timing problems. His current interests are in the areas of precision timing references, jitter attenuation, and frequency synthesis. Prior to his current role, Jagdeep was an integrated circuit designer for 30 years specializing in low noise frequency synthesizer design. Jagdeep has a BSEE and MSEE from UC Davis.
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