Scan diagnostics play an important role in improving yield.
As technologies move below 130 nm, the IC industry has seen a significant change in the type of defects encountered. Feature-related defects are becoming more prevalent than particle-driven defects in nanometer designs. Due to lithography hardware constraints and shrinking design geometries, resolution enhancement techniques such as optical and process correction are necessary but increase the difficulties associated with production ramp and yield learning.
Improving yield in the nanometer domain requires solutions from design through manufacturing. Design for manufacturing (DFM) is one of the important methods to help enhance yield.
Traditional in-line inspection techniques often cannot detect defects due to DFM marginalities that can lead to yield loss. Additionally, fabless companies may not have access to in-line data for driving yield learning. As a result, yield engineers must rely on information gained from parametric test and wafer sort to achieve yield goals.
Moving from left to right in Figure 1, the design becomes less flexible in each design stage. Conversely, engineers gain greater understanding of the manufacturing process and issues once data is available from manufacturing test.
Quick yield learning and the development of DFM rules that can be applied to future products are essential to a robust and manufacturable process. Analysis of memory yield loss has long been the primary driver of back-end yield analysis. Memories typically are routed in regular arrays in the lower poly and metal layers.
DFM marginalities that affect logic routing or only upper metal layers must be identified with tools that can diagnose logic failures. Scan-based diagnosis is the best alternative for detecting systematic and random yield loss affecting logic circuits.
A Yield-Friendly, Scan-Based Diagnostics Solution
Scan diagnostics is based on test patterns from an automatic test pattern generation (ATPG) process and failure information from automated test equipment (ATE). Figure 2 shows a scan diagnostic flow that is beneficial for improving yield. Its capabilities include the following:
• Incoming data consistency check
• Fault model independent analysis
• Suspect classifications in both chain and logic diagnosis
• Diagnosis of compressed patterns
• Configurable reporting mechanism ranking and scoring on pins, nets, and cells
• Production-line diagnosis for large volumes of data
• Linking the failure information with physical locations
• Storing the results in a database format with links to other yield tools
Input Data Checking
The inputs to the yield-friendly scan diagnostics flow include the logical netlist, cell models, test patterns, and failure information from the ATE. Valid diagnostics results depend on inputs that match the environment used for ATPG. Resimulating the pattern inputs with the diagnostic environment provides verification that no changes have occurred from the original ATPG environment.
One of the most difficult steps in preparing for diagnostics is converting the ATE fail file into a consistent format that can be read by the diagnostic tools. Tester differences, extra clock cycles, combinations of functional and scan vectors, and variations in when outputs are strobed can lead to incorrect fail file inputs that will render unreliable diagnosis results.
Additionally, incorrect ATPG inputs also can lead to mismatches between the diagnostic environment and the fail file. The test pattern and failure-file consistency check make sure all the input data is compatible, and in case of an inconsistency, it can pinpoint where the problem is. It's a critical step that is easily ignored and can result in incorrect analysis results.
Accurate logic diagnostics relies on valid data from the scan chains. The flip-flops, clocks, and enable lines that comprise the chain structures can cover 15% to 30% of the logic area and contribute in a corresponding amount to the yield loss at wafer sort.
Diagnosing chain failures requires complex algorithms and large amounts of data in the fail file. Collecting this level of data often is not compatible with yield efforts due to test-time impact.
The first step toward diagnosing chain faults is to look for systematic issues based on the percentage of failures on each chain vs. the length of each chain. Random defects that affect both scan-chain test structures and functional logic are better addressed with standard logic diagnostics. Identification of systematic faults in scan chains often leads to engineering efforts to collect larger amounts of fail file data or implement custom patterns that will provide better diagnostics with fewer fail cycles.
Diagnosis of systematic chain failures first involves identification of the type of potential defects (suspects) affecting the chain. Suspect types include stuck-at; slow-to-rise, slow-to-fall, slow; and fast-to-rise, fast-to-fall, fast.
It is not uncommon for a systematic defect to affect multiple sites with common physical characteristics or span multiple scan chains. As a result, the diagnostic engine must be able to diagnose multiple defects per chain and multiple defects on multiple chains.
Logic diagnosis is performed if the device passes the chain test but fails the logic portion of the scan patterns. Logic diagnostics depend on a set of algorithms that identifies potential defect locations based on the failing chains and flops.
The first step in a yield-friendly diagnostic algorithm is to separate distinct symptoms that are caused by multiple defects on the die. Next, each symptom is diagnosed to identify suspect fault locations. The complexity of the design and the amount of fail information provided to the diagnosis tool can affect how many suspect locations are diagnosed for each symptom. Diagnostic engines that are fault-model independent can identify multiple suspect faults on a single device and various suspect types:
• Stuck-at: includes both stuck-at-0 and stuck-at-1
• Open/dominate: open at the interconnect and weak driver (victim) affected by a strong driver (aggressor)
• Bridge_2way: two nets interacted with each other, such as bridge_and and bridge_or
• Bridge_3way: three nets interacted with each other
Fault-type information can aid the failure analyst in identifying the defect and be an important tool for developing background information about the process. Yield efforts can be focused on the background mechanisms or on rogue lots that deviate from the norm.
Compressed Pattern Diagnosis
The test challenge is to reduce the number of defects-per-million devices. More and more test patterns typically are generated to achieve this goal.
The exploding test volume is limited by test hardware and test time. Test-pattern compression can overcome these limitations.
The compressed patterns, however, introduce an additional level of difficulty to traditional scan diagnosis. It is not uncommon for devices with hardware-based pattern compression to provide a bypass mode so uncompressed scan patterns can be applied directly to the scan chains to aid diagnosis.
For yield learning, using nonproduction patterns is not a practical solution. Retesting wafers with custom pattern sets solely for diagnostics is cumbersome and expensive. The yield-friendly diagnostic flow can provide results on either compressed or uncompressed production pattern sets.
Using limited fail data sets from production often can lead to diagnostic results that identify many potential fault locations. To meet the challenge of diagnosis on production fail data, ranking and scoring of fault suspects are necessary in both chain and logic diagnostics. Ranking lists all the possible defects in the most likely order, and the score indicates how accurately the simulation results match the fail file data.
These features provide better focus for failure analysis work in first silicon debug, yield ramping, and customer return analysis and noise filtering in the yield learning stage. The capability to filter diagnostic results based on suspect type, confidence score, and identified nets from many dice is essential for establishing background yield patterns and identifying systematic issues.
Linking to the Physical World
Once the ranked and scored suspects are determined, the next step is to link the failures in logical domain with the physical database. Physical information on systematic fail locations can help pinpoint particular layers, layout features, or die locations to focus debug efforts. Physical diagnosis information also can be combined with in-line data to help filter yield-limiting defects from background noise. Figure 3 shows a typical application.
In both the first-silicon and yield-ramping stages, it is not unusual to find physical features that are more prone to fab defects than others. Scan test patterns designed to detect specific fault types may be required to analyze these faults.
A robust test set may contain patterns designed to identify a mix of stuck-at, transition, path delay, and bridging faults. With the transition and multiple detection models, bridges and other types of defects can be identified, but the efficiency of the patterns can be improved by targeting specific areas.
Yield-friendly scan diagnostics can help. With the classification and link to the physical layout information, specific areas (nets or layers) can be targeted based on DFM rules.
An example of this is the identification of bridged nets and comparison to rules for net-to-net, via-to-via, or end-of-line spacing. With this knowledge, deterministic ATPG bridging patterns then can be created to improve test quality on all nets with suspect features.
Production-Line Diagnosis on Volume Data Sets
In the yield-learning phase, large volumes of data are required to identify yield trends and focus yield-improvement efforts. Diagnosis on a single prototype lot may be needed one week followed by dozens of production lots the next week.
The yield-friendly diagnostic tool must be able to schedule work to provide the most meaningful data as close to real time as possible. A fast diagnostic engine and the capability to distribute jobs across multiple processors from a single server are required. An interface also must be provided to prioritize lots that show unusual yield signatures or meet other requirements from yield engineering.
Focusing Yield Learning
The next step for yield learning is the capability to store and extract diagnostic data in a friendly format that can be linked to other tools. Creating trends of defect types, physical locations, and frequency will establish background yield patterns. Lots that yield below goal or exhibit unusual patterns then can be analyzed for shifts in defect type or location across the wafer.
This example comes from a 0.11- m technology with six layers of copper interconnect and low-k dielectric. The metal stack consisted of five thin metal layers for signal routing and a thick top layer for power and ground.
The technology had been in production for some time, using up to three thick metal layers to better distribute the power and ground routing. This was the first device to use fewer thick metal layers for cost-reduction purposes. Figure 4 shows a wafer map from the first production lots.
green die scan chain fails, and light blue logic fails.
Although the predominant failure mode was scan-chain failures, the problem was addressed by analyzing the logic failures on the edge of the pattern. Historic data from other devices showed that most scan failures could be attributed to open/dominant type faults. The logic fails from the edge of the center yield pattern were predominantly attributed to stuck-at-0 type faults.
Twelve dice from one wafer were analyzed using the scan diagnostic tool, and 23 faults were identified. A common fault was present on six dice, and most of the nets had routing in Metal 5. Failure analysis efforts were focused on the systematically failing fault, and a bridge to VSS was pinpointed in the Metal 5 layer.
Figure 5 shows a cross-sectional view of the Via 5/Metal 6 defect that was identified as the source of the bridge. The Vias in the array were misshapen due to etch loading during Metal 6 trench formation. This issue was quickly identified with the scan diagnostics, and an adjustment was made to the etch recipe to improve yields on future lots.
and the Via is part of a VSS stack between Metal 6 and Metal 1.
The yield-friendly scan diagnostic flow can accelerate production ramp and identify DFM sensitivities that result in systematic yield-loss mechanisms. Yield-friendly scan diagnostics include a set of verification tools to confirm the integrity of the diagnosis inputs and the capability to diagnose both scan-chain and logic failures and provide meaningful information about the suspect type and confidence of the diagnostic results.
Volume collection of fail data using production-scan pattern sets of either compressed or uncompressed data is essential to detect systematic fail mechanisms. Links to the physical design database can provide an additional level of analysis that can be applied to identify potential defect locations and drive ATPG enhancements.
About the Authors
Keith Gallie is a staff engineer for failure analysis methodology at LSI Logic. He has worked in the semiconductor industry for almost 20 years holding various positions in manufacturing and R&D. LSI Logic, 1621 Barber Lane, Milpitas, CA 95035, 408-954-3108, e-mail: [email protected]
Wu Yang is a technical marketing engineer for DFT products at Mentor Graphics. His technical interests include DFT, BIST, ATPG, and defect-based testing. Wu Yang has an M.S.E.E. from Portland State University. 503-685-0304, e-mail: [email protected]
Nagesh Tamarapalli is the project manager for diagnostics products at Mentor Graphics. His research interests include memory BIST, logic BIST, ATPG, EDT, and defect-based testing and diagnostics. He received a Ph.D. in electrical engineering from McGill University. 503-685-1336, e-mail: [email protected]
Mentor Graphics, 8005 SW Boeckman Rd., Wilsonville, OR 97070.