This is the last article in a three-part series discussing the likely impacts of next-generation consumer wireless semiconductor devices on ATE performance requirements. The first article, which appeared in the October issue of EE-Evaluation Engineering, examined the structural differences between device generations to suggest the likely impact presuming use of existing RF ATE. The second article, in the November issue, discussed the impacts of new capabilities of next-generation devices on instrument performance requirements.
Table 1 summarizes a number of performance-related factors discussed in the first and second parts of this article.
Technology-oriented businesses tilt toward change. As old challenges are met, new opportunities and their associated challenges emerge. Within the consumer wireless industry, two dominant trends are driving significant changes in device functionality and performance: cost reduction through integration of previously separate components and increased channel density and data throughput capacity. Accelerated changes in both dimensions are occurring in next-generation wireless devices.
Next-generation consumer wireless devices support additional carrier frequencies, allowing coverage support with 2G cellular networks during construction of 3G networks. This will occur again in 4G cellular multiple-input multiple-output (MIMO) technology, which necessitates doubling receive and transmit RF pin-counts. The 2G tester cannot test next-generation devices without reducing site-count.
The time required to test the additional RF paths at least doubles the required time on the tester. 3G devices support simultaneous transmit and receive operation; however, 2G testers, built for serialized control and data acquisition, lack the capability to fully exploit concurrent test operation. Not only is site-count effectively halved, but the test time also is roughly doubled. This yields a quadrupling of test cost and a 75% reduction in unit capacity for installed 2G testers.
Greater RFSOC integration and channel count also increase digital pin-counts. RF transceivers only need minimal digital control functions because they are primarily RF-to-baseband analog converters. A handset's digital baseband chip has 150 to 250 digital pins, and these devices are being combined with RF transceivers in RFSOC and RFSIP form. As handset functionality in-creases, so does the digital pin-count.
Integration of digital with RF reduces overall physical size and yields savings in fabrication and packaging costs. The amount of test time needed typically increases because devices do not support concurrent digital scan and RF testing. As high-volume chips move to 45-nm and 32-nm process nodes, the increased prevalence of soft faults, as opposed to hard faults such as stuck-at failure modes, will further increase test requirements.
New standards increase modulation complexity substantially. Tests for error vector magnitude, spectral conformance, and blocker sensitivity drive DSP requirements for which 2G testers were not originally constructed.
The centralized, host-limited control architecture of 2G testers lacks an efficient means of running signal-processing functions in background behind other tests. Data traveling from capture instruments into host processing is an additional bottleneck, which can significantly reduce parallel efficiency.
Since the test times are unlikely to be shortened, it is essential that next-generation device testing be implemented with a much higher level of multisite. You cannot merely upgrade instrumentation as a way out of this cost problem because a fundamental change in the tester architecture is required.
Combinations of one, some, or all of these device changes have a multiplicative effect on the cost of test. As a result, costs will increase if next-generation devices are confined to a 2G tester architecture.
Synthesis With Technological Impacts
The performance differences between current-generation and next-generation devices further emphasize this point. The second article in this series dealt with performance increases required to support larger channel and data capacity, often expressed in terms of bits/second/Hertz. At the device level, this is embodied in ongoing increases in carrier frequency, bandwidth, dynamic range, extends high-speed serial digital, and modulation complexity. Each extends test requirements well beyond the specified capability of 2G testers.
Process change also impacts test system needs. The many added functions in an RFSOC make device debug and characterization using traditional benchtop equipment far more time-consuming.
Not only are the devices more complex, but challenges in front-end process validation also increase the device sample size from tens to thousands. Development teams risk delaying the release schedule if the RF ATE tester lacks laboratory-grade performance correlation.
Reducing Costs
Without a new approach to RF ATE, each of the device changes and new performance requirements will increase costs. The increased RF and digital circuits add to test time and increase the required tester configuration. Added performance might require more costly instrumentation and interface board circuits. A new solution is needed.
An RF ATE system is made up of three major capital asset groups: the handler, the base system, and the instruments, which are categorized as DC, AC, RF, and digital. For RFSOC tests, the price profile is dominated by the handler and kits, the test system base, and RF and AC instrumentation; additional device sites can be added by increasing the relatively inexpensive DC and digital instruments.
The premise behind arguments framed as “sites can be added cheaply” or “just upgrade the existing tester” is a presumption that additional device sites will increase throughput. This, however, is only true in the case of an RF ATE architecture with the highest parallel efficiencies across the combined instrumentation. Such a condition is unlikely and unproven in a 2G tester.
The cost impact of differing parallel efficiencies is illustrated in Table 2. Three equally priced testers support single-site operation for $1.1M including the handler and interface. Adding sites requires an additional $100k per site. The total single-site test time of 5 seconds for the most efficient tester is apportioned into the percentage of time for analog, DC, RF, and digital instrument functions, with digital dominating the overall test time.
The variable in this analysis is the efficiency of the various instruments. Each tester has similar analog and digital parallel efficiencies, but the DC and RF parallel efficiencies vary more significantly. Test times are recalculated according to the weighted average parallel efficiency for each instrument type.
The average efficiencies of the testers–95%, 88%, and 81%–have small deltas because of the small percentage of test time occupied by the more variant DC and RF instruments. However, even small parallel efficiency deltas can have a powerful cost impact.
At single-site, each tester has an unacceptably high cost of test (COT) of more than 30 cents per device. At dual-site, all of the COT values improve. Accordingly, the COT differences among the 95%, 88%, and 81% efficient testers begin to increase. At octal-site, the widest differences are achieved with the 81% efficient tester being 142% more costly than the 95% efficient tester.
The 81% efficient tester reaches its lowest COT of 19.4 cents at quad-site. The octal-site COT of 20.1 cents is higher because the architecture of the 81% efficient tester is insufficient to overcome the price increase of $400k between quad- and octal-site.
Both the 88% and 95% efficient testers show continued cost reduction through octal-site. However, at less than 11.7% COT savings between quad- and octal-site, the 88% efficient tester might not adequately justify the engineering expense of moving to a higher site-count.
The 95% efficient tester yields superior results. The COT for quad-site is 41% greater than octal-site. The COT for the 88% efficient tester is 63% greater. This is a very large COT difference between testers otherwise identical except for a 7% difference in parallel efficiency.
Practical Example
Not all testers are priced identically. In Figure 1, a green tester and a blue tester have differing pricing and throughput characteristics. Assumptions in this example include identically priced handlers and handler kits at $250k and the addition of sites at a price of $75k per site.
The blue tester has superior parallel efficiency of 97.4% compared to a respectable, but lower, 89.2%. The green and blue testers have test times of 4 and 3 seconds, respectively, approximately the inverse of the tester's respective prices excluding the handler and kits.
The green tester appears to have a significant advantage; at quad-site, the green has a lower price and a greater throughput than the more costly blue tester's dual-site. The blue tester has greater throughput at quad-site, but the workcell price also is higher. If the annual volume were never to exceed six million units per year, the green tester might be the best choice, assuming the impact of future resale value is ignored.
If the volume requirement is larger than the capacity of a single workcell, a very different picture of the price of the workcell or capital expense (CapEx) emerges as shown in Figure 2. For the green tester, multiple quad-site configurations are purchased to satisfy annual demand. For the blue tester, both octal-site and 16-site CapEx curves are drawn.
At a demand level of 50M units, the required CapEx for green testers is more than twice that needed for blue testers. If we consider a specific budget, the blue testers deliver 120% greater capacity than the green testers.
Referring again to Figure 1, we now can see the concept of capital efficiency, which can be articulated as workcell throughput divided by CapEx at any data point on the graph. Drawing a line from the origin through any given data point describes the capital efficiency. The steepest slope is the most efficient.
Figure 3 illustrates the economic differences of the workcell's relative throughputs, which are determined by a comparatively small 7% parallel efficiency difference. Small differences in parallel efficiency have a significant impact on the number of testers required for a given capacity requirement. This results in a difference in the required device interface boards (DIBs) and the five-year operating costs for that capacity. In this case, the cost of DIBs and operational expenses for the green testers exceed the CapEx needed for blue testers.
Choosing a Path
A critical question involves where industry should apply its future efforts. Should the needed capabilities be added to existing, fully depreciated testers as a way of avoiding expense? Should new built-in self-test (BIST) techniques be invented for next-generation devices, standards, and fabrication technologies? Or, is a new, more highly parallel tester architecture needed?
For current owners of RF ATE, upgrading existing, low-efficiency 2G testers sounds like a good way to minimize the near-term capital budget. This approach may work temporarily because next-generation device volumes still are relatively small against the more than two billion consumer wireless devices being built in 2007. Excessively high test costs are masked by the much larger volume of simpler RF transceivers.
However, new consumer wireless volumes are growing rapidly. According to Gartner forecasts, 2G device volumes will begin to decline in 2007. Starting in 2008, consumer wireless growth must be driven by next-generation devices. Using a high cost test approach will not be economically feasible in that environment.
Consider that by 2011, six billion RF devices will be built annually, increasing from five billion in the prior year. Year-on-year growth will be a billion devices–devices that are more complex than those filling the existing capacity. Mere upgrades cannot solve the RFSOC COT problem.
Design-for-test (DFT) techniques have been very helpful in reducing logic test costs. If stuck-at state fault models capture a high enough percentage of the failure conditions, DFT will continue to be an adequate test strategy. If the fault model changes to soft faults, the low-speed scan will be unable to identify faulty devices. Some at-speed test may well be needed due to the prevalence of soft faults at 65-nm and smaller geometries.
In RF and analog circuits, there has been some success in creating device-specific approaches to reduce the time needed for RF testing. For extremely high-volume chip designs for mature radio standards, design time and budgets may support the additional resources needed to make RF BIST routinely production-worthy.
For the latest RFSOC designs, the time and investment needed may not be practical. RF devices are highly regulated, and change is rapid. These factors imply an ongoing challenge in developing a universally robust approach to internal RF test.
The case for developing high-efficiency, next-generation workcells is evident. So when do you consider a more efficient tester?
Depending on next-generation device volumes and the growth expectation, an incremental or step function improvement may be desired. At the end of the incremental approach, perhaps the desire to achieve the lowest possible test cost results in the same solution as the step-function approach but without the risk of invention.
Incremental solutions have risks as well. As a result, the best path to a next-generation solution may be to target a step-function solution that can be achieved in a step-by-step fashion so production costs can be moved along the best curve(s) as volumes and cost pressures require.
Conclusion
The rapid growth of consumer wireless continues unabated. As average selling prices of mature RF standards decline, new capabilities and integration levels progress on a seemingly endless innovation cycle. RF trends in both device functionality and performance requirements are expanding simultaneously in next-generation devices. Each of the changes tends to increase costs. Step-function improvement in CapEx efficiency requires new RF ATE approaches achieving higher parallel efficiency.
About the Author
Ken Harvey is responsible for the RF product line architecture at Teradyne. The 20-year veteran of the ATE industry has a background in RF/microwave and graduated from the University of Akron with a B.S.E.E. and Santa Clara University with an M.B.A. Teradyne, MS 600-2, 600 Riverpark Dr., North Reading, MA 01864, 978-370-3670, e-mail: [email protected]
