If you need to transfer data at rates above a couple hundred megahertz, use a serial link. There are several to choose among including the many Ethernet versions, PCI-Express (PCIe), SAS, SATA, USB, and DisplayPort. Most of these standards have been upgraded at least once and today operate at bit rates ranging from DisplayPort's 3.2 Gb/s to 10 Gigabit Ethernet at 10.3125 Gb/s. Both 40-Gb/s and 100-Gb/s Ethernet are under development, so you can expect bus speeds to increase well beyond present values.
A recent change has been the increasingly common use of gigatransfers/s (GT/s) in place of gigabits/s (Gb/s). To maintain a constant average DC level, many serial buses with embedded clocks encode data using an 8b/10b method. Ten bits of transmitted data represent eight bits of real data, the extra two bits being used to balance the number of ones and zeros. Although a link carries signals at a 5-GT/s rate, the information is only going at 4-Gb/s.
The protocols associated with the various standards differ because each type of bus has been optimized for a particular set of applications. Also, the terms and procedures used to define performance seldom are the same from standard to standard.
This variation can result from a viewpoint that favors either the time domain or the frequency domain, reflecting the backgrounds of the industry members that framed the standard. Or, changes in meaning may simply show the refinement of concepts over time. Regardless of how parameters are defined, the basic physics of high-speed data transmission affects all serial buses.
A great deal of the detailed performance verification specifications associated with serial data bus standards relates to signal integrity issues. The fundamental problem is that the communications channel has limited bandwidth. Higher quality PCB material could be used, for example, to reduce high-frequency loss but at greater cost. Instead of improving the channel, most standards describe ways to compensate for its performance.
Losing the Fast Parts
It's easy to show the effect that a limited bandwidth channel has on a fast pulse. Figure 1 is typical of the reduction in amplitude and widening in time caused by a limited bandwidth channel. And, there's a trade-off between channel quality and distance. Even a very good quality channel limits the distance that data can be transmitted before becoming seriously degraded. As distance increases, the high-frequency pulse edges are attenuated more, and this is clear from a plot of channel frequency response.
If, instead of data with its variable mark-space nature, you were transferring a square wave clock across a channel, the problem becomes much simpler. The clock is symmetrical so its DC level isn't affected, just the high-frequency edges. Real data suffers from duty-cycle dependent (DCD) DC offsets.
A standard method used to counteract attenuation that increases with frequency provides compensating frequency-dependent gain. This is done with a filter either at the transmitting or receiving end or both. At the transmitting end, the process is called pre-emphasis because it boosts high frequencies ahead of the lossy channel. At the receiving end, it is called equalization because it compensates for the channel losses.
Actual serial data is not as simple to deal with as a square wave. As Figure 2 shows, depending on the value of the previous bit or bits, the DC level of the present bit will be affected. The effect of one bit on another that results from bandwidth-related attenuation and broadening is called intersymbol interference (ISI).
The overall result can be as drastic as a completely closed eye. It still might be possible for a receiver with equalization to determine the intended data value, but chances are that the bit error rate (BER) would suffer. Serial communications links measure SNR indirectly in terms of BER. After all, it's the error rate that matters, and for most serial links it needs to be at least 10-12 or no more than one error in 1012 bits transmitted.
Crosstalk and ISI
Although ISI is an important source of data errors, it's not the only one. Crosstalk is caused by coupling from another signal and affects both amplitude and timing. Jitter could be caused by the same coupling mechanism or a variety of other causes but affects only timing. Anything that increases jitter or crosstalk results in a more closed eye diagram.
Crosstalk occurs among signals at either the transmitting or receiving end of a link. At the transmitting end, pre-emphasis to correct ISI can boost levels by 6 dB or more and unintentionally add to crosstalk. This is one reason that equalization at the receiving end might be favored as an alternative. On the other hand, pre-emphasis increases signal high frequencies before the addition of channel noise. Equalization boosts high-frequency noise as well as the channel's high-frequency response.
Pre-emphasis may not be practical if the maximum transmission power already is being used. Instead, de-emphasis can accomplish a similar change in level between initial transitions and following bits. In either case, the first bit in a string of consecutive ones or zeros is at a significantly larger level than following bits.
Both pre-emphasis and de-emphasis reduce the effect of ISI, but at the same time they increase jitter. The creation of bits with greatly varying levels and edge rates moves the threshold crossing points from their original positions. At the receiver, the crossing points will have shifted back approximately to their intended positions. But for transmitter testing, some standards offset and scale the data to account for so-called emphasis jitter.
Accurate impedance matching on backplanes is more difficult to maintain at high bus speeds. Vias that are transparent at lower frequencies can cause impedance variations that lead to reflections. And, unless the two striplines that form a differential pair are treated identically, common-mode noise can contribute to noise on the differential signal.
Ideally, a PCB layout will keep both lines on the same layer, next to each other, and as straight as possible. With careful attention to stripline geometry, performance can be very good. Deviations from the ideal contribute to channel degradation, sometimes in very subtle ways.
For example, there are at least three ways to treat connections among or between PCB layers. An ordinary plated through-hole via connects all the way through a PCB. In addition to the outer layers, it may connect to any of the inner layers as well. The main thing is that it goes all the way through the PCB. A blind via is open on one of the outer layers but ends part way through the board. A buried via only connects inner layers and is not open to either outside layer.
Each of these vias has a different effect on trace impedance. A through via that connects only an outside layer and the next layer acts like a transmission line stub because there's about 0.050″ of the via that protrudes beyond the inner layer it's electrically connected to. One way the high-speed performance of boards with through vias can be improved is to carefully back-drill the vias to remove this extra stub material.
Facilitating a Better Decision
In addition to pre-emphasis, de-emphasis, and equalization, which are similar types of filtering, decision-feedback equalization (DFE) can be used to deal with DCD and ISI effects. Various algorithms, some linear and some nonlinear, are used to correct the DC offset that results from groups of ones or zeros.
Although the algorithms can be complex, a simple DFE might compute the average of the last four bit levels, invert and delay the result, and add it to the signal. As in the case shown in Figure 2, the idea is to minimize the effect of previous bits on the level of the signal. If this is done well, a much greater margin is created between the signal level and the threshold to which it's being compared. The result is a higher SNR and a lower BER.
Spread Spectrum Clocking (SSC)
Why would anyone intentionally introduce jitter into a system? This is a valid question because SSC is exactly that: designed-in jitter. SSC has become a popular way to reduce EMI by spreading the energy associated with fast clock edges.
EMC standards specify the radiated and conducted maximum levels that a piece of equipment can generate. Although designers may attempt to reduce the overall energy density at all frequencies, many systems dither the clock frequency by a few percent to further minimize fast clock harmonics. As the clock frequency is modulated, the harmonics follow, and the maximum energy at any one frequency is reduced.
Recovering the Signal
After compensating for the channel effects, the recovered data must be interpreted by the receiver. Was a one sent or a zero? Because the clock is embedded in serial data systems, a PLL is used to recover it and establish the best time to sample the signal. Assuming that the loop does its job, how does it react to signal jitter?
This is another standards area that attracts a great deal of detail. Jitter moves the decision point timing, so rather than the receiver comparing the signal to the threshold at the optimum point, the decision will be made at a slightly different time. Jitter within the loop bandwidth is filtered out. Jitter outside the loop bandwidth is not. So, the loop bandwidth and its rolloff characteristics are two more parameters to be adjusted for the best performance.
Because many impairments affect serial data, it makes sense to test transmitters and receivers and complete links with some prescribed level of ISI, crosstalk, and mixtures of types of jitter. This concept is simple enough, but it has taken manufacturers time to reach widespread agreement on jitter decomposition and measurement.
Guy Foster, the vice president of outbound marketing at SyntheSys Research, listed various types of impairment and their application:
• Sinusoidal Jitter (SJ): Primarily used to exercise the clock recovery.
• Random Jitter (RJ): Sometimes frequency banded as in PCIe and usually expected to be truly random down to probability levels of at least 10-12.
• Bounded Uncorrelated Jitter (BUJ): Used in some standards to emulate the effects of crosstalk and achieved by jittering the pattern generator's bit edges with a pseudorandom binary sequence (PRBS) modulation.
• SSC: Modulation of the clock and data output of the pattern generator with a low-frequency variation that must be tracked by receivers and is emulated in stress testing with a fixed amount of SJ. SSC generation by the device transmitter and handling by the receiver are the most frequent causes of failures in compliance testing for standards such as PCIe.
• ISI: Many standards require that the receiver be tested after the test signal has undergone the kind of degradation that would come from a channel typical to the system type being designed for. This usually is a particular frequency response obtainable from a given length of circuit board but can be more complex for standards such as 802.3aq, the long reach multimode (LRM) variant of 10 Gb/s Ethernet.
• Multitap Pre-Emphasis, such as for Backplane Ethernet, 10GBASE-KR.
Now that test methods used by different manufacturers yield similar results, stressed-eye testing has become commonplace. One way to accomplish it is by literal implementation of the standard. If some RJ is needed, an RJ generator adds a calibrated amount to the signal. The same is done for SJ, periodic jitter (PJ), BUJ, ISI, and SSC.
Although it's difficult to know exactly how a particular instrument works in detail, Agilent Technologies describes the company's J-BERT N4903A Pattern Generator as though it were a literal implementation: “The…generators enable fast and accurate testing by simplifying worst-case jitter tolerance testing with built-in and calibrated jitter sources for RJ, PJ, and BUJ [and by] emulating ISI, [and by] injecting commonly used SSC.”
SyntheSys Research has developed versions of the BERTScope™ that also have this capability. As explained by Mr. Foster, “A model has been introduced that contains stress elements useful in most standards but particularly targeted at PCIe, which has several unique requirements. A companion instrument, the four-tap Digital Pre-Emphasis Processor (DPP), covers the new 8-GT/s PCIe and 10-Gb/s Ethernet backplane 10GBASE-KR (802.3ap) standards and beyond.
“As with many areas of testing, a key to accurate measurement results is the calibration of the system,” he continued. “In this case, it means being sure that the impaired signal is correctly constructed and stressful enough to comply with the standard but not overly stressful so that healthy devices fail. This means calibrating at the end of the test cables that are to be connected to the device being tested. The BERTScope analyzer function offers many views of the signal, giving an accurate indication of low-level BER performance.”
Both the Agilent and SyntheSys Research instruments can provide a complete serial bus test solution including a stressed-eye pattern generator together with receiver emulation and BER test capabilities. However, there are other approaches to the problem. Tektronix has developed very high rate Arbs that can directly generate a test signal.
In spite of the various kinds of impairments affecting transmitted data, only one signal exists at the transmitter output or receiver input. With the right data file and a sufficiently high bit rate, a fast Arb can simulate any combination of jitter, crosstalk, SSC, and ISI. The company terms this approach direct synthesis. Specifying the combined effect of all these elements is complicated, but with Tek's SerialXpress® Signal Design Software and preprogrammed examples, it's actually easy to do in practice.
Bob Buxton, the company's marketing manager for the signal source product line, said, “A traditional digital pattern generator does not have the required functionality and performance to conduct either margin testing in a design validation or debug environment or perform compliance testing against the standards. Instead, what is needed is a way to generate the signals, complete with known impairments, in a way that is simple, flexible, and repeatable.”
On the plus side, using an Arb in this way provides the additional capability of importing S-parameter files to emulate cables or test fixture effects. This means that you can explore the results of increased cable length or a different type of cable, for example.
On the down side, an Arb is only a signal source, and you will need additional test equipment to determine BER and performance margins. Mr. Buxton said that Tek addressed compliance testing through an automation framework called TekExpress™. This is a software application that brings together your assembled test instruments as a fully automated test system for SATA receiver, transmitter, and interconnection testing.
Regardless of which solution you may use, it's important to understand the advantages of pseudorandom signals for this type of testing. The difference between a truly random signal and one that is only pseudorandom is that the pseudorandom one repeats. On the other hand, the period required to run through all possible states of a PRBS can be several days even at a gigahertz rate.
A PRBS designed for low-BER testing is equivalent to a truly random source down to at least the 10-12 level. However, the PRBS can be restarted at precisely the same point used to start the previous test. You can be certain that the present test will be stressed in exactly the same way as the previous test. This isn't possible if a truly random noise source is used, especially when some errors may relate to ISI effects caused by specific bit pattern history.
Replacing parallel buses with high-speed serial links does have advantages. Especially at speeds below a gigahertz, serial links eliminate clock-to-data and data-to-data skew errors associated with parallel buses without adding too many new problems. This same free lunch can't be claimed for the newer 5-, 6-, and 8-GT/s standards, but parallel buses no longer are practical alternatives at these speeds.
Guaranteeing compliance given the high rates and stressed patterns associated with newer standards demands extreme instrument performance and a methodical test approach. With very high-speed buses, data transmission closely resembles RF. Test techniques become at least as important as the test equipment capabilities because it's so easy to degrade instrument performance. Without sufficient attention to test setup details, how can you hope to determine if an error has been caused by an actual signal anomaly or reflections from a slightly loose connector?
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