Date: Tuesday, November 27, 2018
Time: 12:00 PM Eastern Standard Time
Duration: 30 Minutes
PCIe Gen5 has the potential to turn transfer rates long considered to be in the realm of science fiction into reality. To discuss the design, test, and measurement challenges associated with this, we’ve assembled a team of industry experts. Our panel will first discuss the applications that are driving PCIe from Gen4 at 16 Gt/s to Gen5 at 32 Gt/s. Next, we will offer methods for meeting the technology and test challenges that are an outcome of a doubling of the transfer rate. The panel will both review the challenges associated with designs at 32GT/s and the tools that are necessary to overcome these design challenges. Hear from a group of experts with significant industry experience, including time spent collaborating on PCIe specification and certification.
Director of System Engineering
Dan Froelich has joined Tektronix as its Director of System Engineering. For the prior 18 years Dan worked as an Intel engineer and architect focused on specification and compliance test methodology development for USB and PCI Express standards. Dan served as co-chair of the PCI-SIG electrical workgroup and technical editor for the electrical specification for the PCIe 4.0 and PCIe 5.0 specification development. Dan also served as chair of the PCI-SIG Card Electromechanical (CEM) workgroup and technical editor from 2005 to 2018 covering the PCI Express 2.0, 3.0, 4.0 and early 5.0 CEM specification development. In addition, Dan served as co-chair of the Serial Enabling (Compliance Program) workgroup from 2007 - 2018 and served as technical editor and technical lead or developer on many of the test specifications and tools used by the PCI-SIG compliance program. Dan also won an Intel Achievement Award as the overall technical lead on the USB 2.0 industry compliance program and wrote the USB 3.0 hub and isochronous protocol specifications. Dan Froelich graduated with honors and high distinction from Harvey Mudd College in 1996 with a BS in Physics. Dan holds 6 US patents with several more applications pending.
Product Marketing Engineer
Jim Dunford is a Product Marketing Engineer in the Tektronix Wideband Solutions group, specializing in receiver test products and applications. Jim came to Tektronix in early 2010 with the acquisition of SyntheSys Research, the BERTScope company, and has more than 20 years of experience with receiver test applications, sales, marketing and customer support.
Engineering Group Director
Cadence Design Systems
Rajkumar manages the Silicon validation and Systems team as part of IPG group at Cadence Design Systems based out of Bangalore. He has over 20 years of experience in Analog, Mixed signal and High speed Serdes Testing. He has a MSEE from Birla Institute of Science and Technology.
Sr. Applications Engineer
Pete Tomaszewski is a Sr. Applications Engineer at Tektronix with over twenty years of experience in high speed serial data design and test applications. Pete Has a BSEE from Rensselaer Polytechnic Institute.