Available On Demand
Sponsor: Mentor, A Siemens Business
Safety-critical designs have typically used either a manual coding approach or specialized FPGAs with built-in protection from single event upsets. However, both of these approaches have several limitations - manual coding is too time-consuming, error-prone and requires expertise in synthesis/P&R tools or the specialized FPGA choice is limited.
In this webinar we will look at automated synthesis-based mitigation methods such as triple modular redundancy (TMR) and safer finite state machine (FSM) encoding - fault tolerant and fault recovery modes, on an FPGA device of your choice.
What you will learn:
- Design considerations for high-reliability/safety-critical applications
- Synthesis-based TMR technology for SEUs and SETs, and how to apply the best TMR strategy for different devices
- Automated methods for encoding finite state machines that detect and correct SEUs
- Methodologies and tool flows to verify design functionality and mitigation effectiveness after synthesis-based mitigation
Product Manager of Precision Synthesis
Mentor, a Siemens Business
Rakesh has over 20 years of experience in ASIC/FPGA design and various EDA tools. Prior to joining Mentor, he has held engineering, product planning and technical marketing positions at Apple, Altera (now Intel) and Synopsys. Rakesh holds a Master’s degree in Electrical Engineering from Stanford University, specializing in VLSI design.