Arteris IP

Campbell, CA 95008

COMPANY OVERVIEW

About Arteris IP

Arteris technology transforms IP blocks into optimized SoCs. Learn more at arteris.com.

Contact

595 Millich Dr.
Suite 200
Campbell, CA 95008
https://www.arteris.com/
+1 408 470 7300

More Info on Arteris IP

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Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration technology enables SoC creation success with proven flexibility and ease for a variety of applications and markets including AI, automotive, communications, consumer electronics, enterprise computing, and industrial. Arteris technology ensures higher product performance with lower power consumption and faster time to market, delivering better SoC economics for its global customer base including semiconductor manufacturers, OEMs, hyperscale system houses, semiconductor design houses and other producers of electronic systems.

The Arteris product line is silicon-proven, supporting SoC innovation from creation to integration.

Network-on-Chip IP Products

  • Non-coherent NoC IP, with FlexNoC and FlexWay
  • Cache-coherent NoC IP, with Ncore
  • Last-level Cache, with CodaCache

SoC Integration Products

  • SoC integration with Magillem Connectivity, Magillem Registers, and CSRCompiler

Articles & News

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Adding Cache to IPs and SoCs

June 27, 2024
Integrating cache memory into SoCs and IP blocks improves their performance and efficiency. This article highlights technologies and strategies to address challenges like cache...
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Functional Safety for Control and Status Registers

May 16, 2024
How to navigate the complexities of building functional safety into SoC design, including managing IP blocks, CSRs, and adhering to standards like ISO 26262.
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Certified Cache-Coherent Interconnect Supports Safety Applications

March 26, 2024
The Ncore network-on-chip design tool developed by Arteris delivers ISO 26262 certification.
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Navigating the Hardware-Software Interface in Chip Design

Jan. 31, 2024
Register-transfer-level (RTL) verification is a critical component to successful chip design.
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Optimize SoC Design with a Network-on-Chip Strategy

Aug. 23, 2023
Utilizing physically aware interconnect IP from trusted third-party vendors can reduce design time and increase productivity.
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Computer-Aided Design

NoC IP Merges with SoC Integration Automation Software

July 24, 2023
At DAC, Arteris featured its system IP, which includes its network-on-chip interconnect IP and system-on-chip integration automation software to help boost product performance...

Videos & Resources

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Physically Aware Network-on-Chip Streamlines SoC Design Cycle

Feb. 22, 2023
The NoC IP configuration tool developed by Arteris IP is designed to optimize layouts while cutting design time.
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Quick Chat

QuickChat: Track Design Changes To Meet ISO 26262 Functional Safety and Other Standards

April 18, 2022
Bill Wong and Paul Graykowski discuss Harmony Trace which enables design teams to monitor impacts to requirements of complex SoCs by creating and maintaining traceability between...

All content from Arteris IP

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Making ISO 26262 Traceability Practical

March 11, 2022
Increase system quality and accelerate functional-safety assessments by identifying and fixing the traceability gaps between disparate systems.