Ever go to a restaurant, sit down to a complex menu, and just wish you had a few choices instead of dozens? If you've recently attempted to decide the optimal ASIC solution to best fit your design constraints, you may have felt similarly overwhelmed with choices. In fact, "configurable ASICs" have several aliases:
- metal/mask programmable/configurable
- via configurable.
Structured and platform ASICs have established themselves as an intermediate solution that nicely fills the big gap between FPGAs and standard-cell ASICs. The main cause behind the widening gap—shrinking process technology—is readily adopted by both ASIC and FPGA vendors.
The process technology shrinkage translates to multi-million dollar non-recurring engineering (NRE) costs for each ASIC design and a higher minimum order quantity. Design and fab processing time are also much higher with standard-cell ASICs. Key benefits derived from using standard-cell ASICs include a significantly lower unit cost, a far superior use of silicon area, lower power consumption, and higher speed.
Platform and structured ASICs bridge the gap by offering minimum order quantities, lower NRE costs, and less fab time than standard-cell ASICs, while providing near-standard-cell ASIC benefits (Table 1). Yet because vendors have been consistently inconsistent with respect to available features, I/O standards, supported protocols, and native and drop-in IP offerings, adoptability has suffered (Table 2). The same can be said for the other types of configurable ASICs.
All structured and platform ASICs provide prefabricated digital logic structures, such as flip-flops, memory blocks, uncommitted usable logic gates, and higher-level building blocks. The logic gates, flip-flops, and higher-level structures can be configured according to desired system functionality.
Once the uncommitted logic fabric is designed, with vendoroffered IP added where applicable, the design is sent to a fab that places one to five metal layers defining application-specific chip functionality on the chip (Fig. 1). Most structured and platform ASICs provide phase-lock and delay-lock loops (PLLs and DLLs), offer one or more protocols, and support multiple I/O standards.
The difference between platform and structured ASICs varies greatly between vendors. Generally, though, platform ASICs are higher-end structured ASICs that offer more features, integrated components, and programmable I/O.
Before you choose a structured or platform ASIC, you should be aware of other options. Perhaps you require a microprocessor and only a small amount of programmable logic. Or, maybe you need a mixed-signal solution. Several other types of configurable ASICs are available:
- Mask-reconfigurable: If you're looking for configurable IP that you can drop into any package, and you'd like to choose I/O standards, logic array size, and embedded tests, consider using mask-reconfigurable IP. Lightspeed Logic has developed technology to build mask-reconfigurable IP. For the configurable I/Os, you have control over the input type and level, as well as output type, level, and slew, allowing you to choose from a wide variety of digital and analog I/O standards. The mask-reconfigurable logic array is available in 90-nm process technology and provides a density approaching a standard-cell ASIC.
- Metal-programmable: It's basically the same as maskreconfigurable technology. Atmel's Metal Programmable Cell Fabric (MPCF) technology is based on 130-nm process technology. Offering over 400 cells and around 170 gates/mm2, MPCF can be integrated with a variety of MCU and DSP cores, along with IP blocks, analog cells, and I/O package options.
- Via-configurable: Designers can customize via masks to implement combinational and sequential logic and SRAM. Triad Semiconductor offers via-configurable mixed-signal ASICs with only a single layer to configure. The analog portion can be configured to provide analog-to-digital and digital-to-analog converters (ADCs/DACs), operational amplifiers, and passive arrays. Digital resources include up to 150k usable gates, a 205-kbit SRAM, and up to 71 configurable I/O pins.
If you've reviewed the options and decided you may want an alternative to a metal-or via-configurable ASIC, consider one of the inexpensive FPGA/MCU solutions. These products offer a nominal amount of programmable logic and come standard with a microcontroller (MCU) at prices that approach standard-cell ASICs. Many of these devices are also in-system programmable via a JTAG interface.
For instance, Cypress has crafted a mixed-signal programmable system-on-a-chip (PSoC) with an integrated Harvard architecture microcontroller. The PSoC devices include up to 32 kbytes of flash memory, 2 kbytes of SRAM, an analog multiplexer, and up to 50 user I/O pins (see "Programmable SoC Delivers A New Level Of System Flexibility," ED Online 4902, at www.electronicdesign.com).
QuickLogic's QuickMIPS family of SoC devices integrates a 32-bit MIPS processor, a memory controller, dual 10/100M Ethernet MACs, and a PCI controller. The one-time programmable fabric includes a 16-kbyte SRAM, up to 2k logic cells, and up to 252 I/O pins. The family natively supports LVTTL, LV-CMOS, PCI, GTL+, and SSTL.
Flash-based programmable system devices (uPSDs) from STMicroelectronics contain an 8-bit 8032 MCU core. These devices come with up to 288-kbytes flash, a 32-kbyte SRAM, and multiple communication protocols.
Actel's latest flash-based FPGAs, the Fusion Programmable System Chips (PSCs), offer an ARM7 or 8051 soft core microprocessor. These devices provide up to 1.5 million gates, up to 8-Mbits flash memory, up to 270-kbits RAM, and up to 278 high-performance I/Os. Also included are one or two PLLs, a 12-bit ADC, several single-ended and differential I/O standards, and up to 10 analog quad-programmable blocks. Each block contains analog functions, including multiplexers, op amps, and analog I/Os.
So now that you have an understanding of what's available in the ASIC market, how do you decide which solution is best for you? You should be able to narrow down your choices using the information in Table 1 and the flow comparison (Fig. 2).
One of the most powerful arguments for using an FPGA involves in-system programmability and reconfigurability, which has some ASIC vendors pondering whether to provide some form of reprogrammability. However, adding reconfigurability to an ASIC takes away some of its size, performance, and power benefits due to the overhead required for the reconfigurable fabric.
For instance, FPGAs like Xilinx's Virtex-5 utilize 65-nm process technology. This gives 90-nm-plus structured and platform ASICs less of a speed and power advantage over such FPGAs. By comparing design flows for FPGAs and ASICs, we can better understand the advantages and disadvantages to each type of approach (Fig. 2, again). The basic flows for each design implementation are quite similar, with some exceptions:
- The I/O design portion is greatly simplified for most ASIC implementations, since there's usually no need to design for I/O signal compatibility at the bank/region level. Designs that require several I/O standards must be compatible within a bank/region with respect to voltage, direction, and termination type. The requirement to have compatible I/O standards within a bank makes it more difficult to spread high-speed signals across banks to avoid issues with simultaneously switching output noise (SSO or SSN).
- Most FPGAs and some structured and platform ASICs don't require design for-test (DFT) implementations, such as scan path, built-in self test (BIST), and boundary-scan via JTAG. These DFT structures are usually built in.
- FPGAs and some structured/platform ASICs don't require design of the global and local clocking fabric. This provides a major time savings advantage in design, testing, and verification of the clock and logic fabric. The main disadvantage to a pre-defined clocking structure is the inherent inflexibility. Local/regional clocks only work with specific logic structures and their associated I/O pins. Figuring out which local/regional clocks work with which logic structures and I/O pins can be challenging and time consuming.
- FPGA design rule checks (DRCs): FPGAs don't need a physical DRC since all of the structures are predefined and pre-verified.
- Before any type of ASIC can be used, it must be sent to a fab. Typically, this requires advanced scheduling of several weeks or months. Also, the completed design implementation must arrive at the fab on time or you risk losing your spot in line. The fact that FPGAs are pre-fabricated gives them an advantage over ASICs, as the fabrication process can take several weeks for structured/ platform ASICs to several months for standard-cell ASICs. So if your entry into the market is timing-critical, consider prototyping with an FPGA and then make the move to some sort of ASIC if the number of units, speed, and other considerations warrant it.
GET READY TO RUMBLE
Looking ahead, it will be fun to watch the structured/platform ASIC vendors battle it out with the FPGA and standardcell ASIC vendors, which usually bodes well for the consumer in terms of pricing, technology, and selection. The structured/platform ASICs should steal more of both the FPGA and especially standard-cell ASIC market shares. In addition, companies like Open-Silicon are providing reduced-price custom ASICs that offer improved predictability and reliability.
Until recently, LSI Logic was a major player in the platform ASIC space with its RapidChip products. The company has since moved on to offering application-specific standard-product (ASSP) solutions. Will other companies follow suit? Also, it's likely that some of the smaller companies will get assimilated by larger ones. Stay tuned.
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