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New LoRaWAN Chips Designed to Handle Dense Networks

Semtech’s new SX126x family reduces power requirements, increases range, and supports the new SF5 spreading factor designed to handle dense networks.

New wireless network chips seem to be cropping up all over the place. Sigma Designs’ 700-Series chipset increases range and uses less power. A sensor can run on a coin-cell for 10 years, even with the built-in ARM Cortex-M processor.

Semtech’s new SX126x family (see figure) targets LoRaWAN, a low-power, low-speed network with long range. LoRaWAN targets applications like smart meters, asset tracking, healthcare, and street lighting, where the technology’s advantages and limitations match the wireless requirements of the systems. LoRaWAN devices can be very simple, as are the gateways, with much of the routing management being done at a higher level that may be in the cloud.

The SX126x family supports the new SF5 spreading factor designed to support dense networks.

The chip family reduce power requirements, increases range, and supports the new SF5 spreading factor designed to handle dense networks. SF5 uses less spreading, allowing faster speeds and short connection times while providing a better connection.

The chips can use 50% less power in receive mode. They can also extend the range of communication by 20% compared to the prior generation. They have a transmit power of +22 dBm. The chips support Class A that is optimized for power consumption, as well as Class B and always-on Class C. The chips also have an on-board DC-DC converter with an integrated LDO. There is a built-in bit synchronizer for clock recovery system, plus automatic channel activity detection (CAD) with ultra-fast automatic frequency control (AFC).

The chip family incorporates a protocol engine that is essentially a dedicated microcontroller. This allows the SPI interface to be used to exchange commands instead of just toggling bits in the modem. This simplified user interface reduces the load on the host processor as well as the developer’s coding chores. Sending and receiving packets can now take as little as 10 lines of C code.

The compact, 4-mm by 4-mm chip supports a frequency coverage of 150 to 960 MHz. It is protocol-compatible with existing deployed LoRaWAN networks.

Chips also support FSK, GFSK, MSK, GMSK, and LoRa modulation. They have programmable bit rates up to 62.5 kbits/s for LoRa and 300 kbits/s for FSK and variants.

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