Altera is taking two different approaches for their mid-range Arria and high-end Stratix FPGA families now in their 10th generation (Fig. 1). Altera notes that this approach will provide the best tradeoffs for each family since Stratix targets high-performance solutions while Arria balances performance with low power requirements.
The Arria 10 is available now but Stratix 10 users will have a longer wait as Intel ramps up production of the Stratix 10 line for Altera. This is because the Stratix 10 will utilize Intel's latest 14-nm technology while the Arria 10 will be handled by TSMC using its 20-nm transistor technology.
Stratix 10 Jumps To 14-nm
Altera will be taking advantage of Intel's 3D Tri-Gate technology that initially used Intel's 22-nm transistors (see Moore's Law Continues With 22nm 3D Transistors). Altera is not the first vendor to take advantage of Intel's 3D technology. Achronix Semiconductor utilized Intel's 22-nm technology for its Speedster FPGA (see 22nm 3D Transistor FPGA Packs In Hard Core IP).
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The Stratix 10 will run at 1 GHz whereas a 20-nm implementation would typically be running at half that speed. Altera essentially jump a process generation while delaying deliver until later this year.
In terms of trade off, the Stratix 10 can deliver the same performance as the current 28-nm Stratix incarnation but using only 30% of the power or it can use the same amount of power while increasing performance by a factor of 1.6. It can also double the performance with a 30% power increase. This provides designers with a range of power/performance options using the same chip.
Other major changes will include support for 56 Gbit/s SERDES. Single-precision floating point DSP support will bump DSP performance by a factor of 10. A chip will be able to deliver 10 TFLOPs of single-precision floating point performance. That is about 100 GFLOPS/W. Overall system density will be increased by a factor of four allowing even larger designs to be built.
Altera hinted at some interesting options that will be available with the Stratix 10. This includes support for multi-die, 3D solutions that could incorporate devices like SRAM, DRAM, and ASICs. This might utilize an approach similar to Xilinx's 2.5D interposer technology (see 10,000 Connections Between FPGA Slices).
The earlier Stratix 9 and the new Arria 10 families support hard IP, dual core, Cortex-A9 processors (see Dual Core Cortex-A9 With ECC Finds FPGA Home). The Stratix 10 will support an unnamed third generation processor architecture. Could that be Intel?
Arria 10 Delivers Hard Cores
The Arria 10 is built by TSMC using its 20-nm technology for Altera. It is designed to be the mid-range solution from Altera to the 10th generation Stratix mentioned above. While power and performance are not in the same realm as the Stratix 10, the Arria 10 blows away the prior generation Stratix V. The Arria 10 will deliver 15% more performance with lower power requirements.
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The Arria 10 will support Altera's 28.05 Gbit/s SERDES. Up to 16 can be found in the high end chips and these also support backplanes when running at 17.4 Gbit/s. FPGAs are used extensively in military, avionic, communication and video applications where backplanes are used to create very large systems.
The new family will handle the lates 2666 Mbit/s DDR4 memories. It is also designed to handle the new Hybrid Memory Cube Consortium's serial memory interface that runs at 15 Gbit/s (see Hybrid Memory Cube Shows New Direction For High Performance Storage). The Hybrid Memory Cube brings very large amounts of storage close to the FPGA with a very high bandwidth data path.
The family will have chips with up to 1 million logic elements (LE). The whips will also use 40% of the power compared to the previous generation.
The Arria 10 will also have options for the hard, dual core, Cortex-A9 platform introduced earlier. The latest platform (Fig. 2) will employ 1.5 GHz Cortex-A9 cores and DDR4 memory interfaces that include ECC support. It can have up to 3 Gigabit Ethernet channels.
FPGA debugging has always been a challenge for developers. Altera's answer is SignalTap, an analyzer-style interface that is integrated with Altera's Quartus II FPGA development suite. The FPGA-adaptive debug support is also integrated with the hard core processors. This allows the FPGA and software debugger to handle single stepping, breakpoints, and other debug options so FPGA logic can be synced with the software. There is a global timestamp for trace capture that can capture all registers. The breakpoints can also trigger a SignalTap logic analyzer trace.
All of Altera's new FPGAs will be able to take advantage of OpenCL. Altera is leading the charge with its OpenCL FPGA SDK (see OpenCL FPGA SDK Arrives). The SDK allows OpenCL kernel code to be converted into FPGA logic while providing a memory management framework to support OpenCL data communication.
Altera's dual approach to its 10th generation families makes sense. Utilizing Intel's production and technology allow Altera to deliver cutting edge performance where price is less of an issue that capability. Using TSMC's tried and tested support delivers FPGAs that are more price and power conscious. The fact that they are better than the previous generation's high end may give designers pause because a lower cost, mid-range platform may make more sense going forward. All of Altera's FPGA families are supported by the Quartus II FPGA development environment.