November 18, 2025
2:00 PM ET | 1:00 PM CT | 11:00 AM PT
Duration: 1 Hour
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Summary
Are you designing a board with high-speed chipsets on either end of the link? You own the interconnect—and the risk. As clock and data rates climb, maintaining signal integrity becomes critical for reliable performance
In this webinar, Dallas Mohler, Senior Applications Engineer at Tektronix, will show how to quickly observe and debug real-world signal integrity issues that arise when integrating SerDes links—like closed eyes, excessive jitter, unexpected noise, and confusing results.
This session is ideal for engineers designing or testing clocks or chip-to-chip communication links across standards like PCIe®, USB, DisplayPort™, MIPI, and Ethernet.
You’ll learn:
- Where and how to probe signals for meaningful insight.
- How to set up clock recovery and when to apply equalization (CTLE/DFE).
- Methodologies to address closed eyes, random vs deterministic jitter, channel & signal path effects, and power rail induced noise.
Tools used: real-time oscilloscopes, jitter and eye analysis, BER estimation, and de-embedding.
Don’t miss this opportunity to discover a repeatable debug workflow you can apply right away, resulting in fewer re-spins and faster bring-up times.
Register Today.
