Inside PCIe 6.0 Receiver Calibration & LEQ Testing
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PCI Express® 6.0 Antegrators List testing is just around the corner. As PCIe technology continues its tradition of doubling I/O bandwidth every three years, it remains the preferred interconnect for AI/ML, high-performance computing, and hyperscale data center applications. However, the move from NRZ to PAM4 signaling at 64 GT/s introduces significant new challenges for PHY validation and compliance testing.
Receiver calibration and link equalization are no longer routine tasks. Engineers commonly face issues with calibration convergence, backchannel optimization, and Link Equalization (LEQ) failures during bring-up and compliance validation.
In this webinar, we will cover practical aspects of PCI Express 6.0 PHY electrical testing based on the latest official test specifications. Topics include achieving reliable receiver calibration, optimizing the backchannel prior to receiver testing, and performing key electrical compliance tests including Receiver LEQ and Transmitter LEQ. Attendees will also learn best practices to improve test robustness, repeatability, and overall compliance success.
What You Will Learn:
- Overview of PCI Express 6.0 receiver electrical compliance testing
- Step-by-step stressed-eye receiver calibration procedures and practical convergence tips
- How to properly optimize the backchannel before receiver testing
- Methods for performing Transmitter LEQ and Receiver LEQ tests
- Best practices to avoid common pitfalls and improve test reliability
Speakers:
Tetsuro Obinata
BERT Product Marketing Manager / PCIe Electrical Test Expert
Anritsu
Tetsuro Obinata has 19 years of experience in high-speed technologies and currently serves as the Product Marketing Manager for BERT products at Anritsu. He spent more than 15 years as an engineer developing high-speed BERT solutions, including PCIe link training and compliance test solutions, leading multiple related projects. He has also built deep practical troubleshooting expertise through active participation in PCIe workshops
Joey Chiu
PCI Express Technology Lead
Tektronix
Joey Chiu is a PCI Express Technology Lead at Tektronix. He represents Tektronix in PCI-SIG standard bodies and actively contributing in Electrical and Serial Enabling workgroups for Base, CEM, and PHY test specification development. Joey's area of focus includes high-speed serial testing, developing transmitter and receiver test methodologies, digital signal processing algorithms, and designing automated test software. Joey receives both his M.S. and B.S in Mechanical Engineering from National Taiwan University.
