Addressing Chiplet Interconnect Design Challenges
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The chiplet market started with custom interconnects suitable for the limited number of different types of chiplets being used a system but the rise of standards like UCIe and BOW are helping to increase the number of distinct chiplets by simplifying chiplet interconnects. Standards are useful but it is the tools, test procedures and architectures that can be built on them that reduce the designers burden when creating chiplets and chiplet-based designs.
This panelist in this session will address changes in the chiplet ecosystem and how developers are using standard interconnects to design their system architectures.
Speakers:
Jim Handy
General Director
Objective Analysis
Jim Handy of Objective Analysis is a 35-year semiconductor industry executive and a leading industry analyst. Following marketing and design positions at Intel, National Semiconductor, and Infineon he became known for his technical depth, accurate forecasts, industry presence, and numerous market reports, articles, white papers, and quotes. He posts blogs at www.TheMemoryGuy.com, and www.TheSSDguy.com.
Moshe (Moshiko) Emmer
Distinguished Engineer
Cadence
Moshe (Moshiko) Emmer is a Distinguished Engineer at Cadence, where he leads the Chiplets and NoC R&D activities.
Moshiko has over 20 years of experience in the hardware engineering industry. Prior to Cadence, he held various managerial and technical leadership positions at Intel Corporation.
Moshiko brings in-depth knowledge of hardware design development, spanning from architecture to high-volume manufacturing.
He holds an MSc. and BSc. (with honors) in Electrical Engineering from the Technion, Israel Institute of Technology.
Tim Wang Lee, Ph.D.
Signal Integrity Application Scientist
Keysight Technologies
Tim Wang Lee, Ph.D., is a Signal Integrity Application Scientist at Keysight Technologies, where he develops modeling, simulation, and validation workflows for high-speed digital and chiplet interconnects.
His work focuses on translating emerging interface standards and system requirements into practical engineering methods for channel analysis, electromagnetic modeling, compliance evaluation, and simulation-to-measurement correlation. He works closely with semiconductor, packaging, and system-design teams to address signal-integrity challenges across advanced packaging and printed circuit board environments.
Tim earned his Ph.D. in Electrical Engineering from the University of Colorado Boulder, where his research focused on building confidence in high-speed interconnect models through measurement correlation. He has authored technical papers, industry articles, and educational content on signal integrity and interconnect design, and was recognized as a DesignCon 40 Under 40 engineer.
Rob Kruger
Product Management Director
Synopsys
Robert Kruger serves as a Product Management Director at Synopsys, where he oversees IP solutions for multi-die designs, including 2D, 3D, and 3.5D topologies. Throughout his career, Robert has held key roles in product marketing, business development, and roadmap planning at leading companies such as Intel, Broadcom, Nokia, and Altera. He brings extensive expertise in semiconductor technologies, including ASICs and FPGA products, as well as deep knowledge of specialized requirements across various sectors, including wireless infrastructure, military, automotive, industrial, and data center markets. Robert holds a Bachelor of Science in Electrical Engineering (BSEE) from Boston University and a Master of Business Administration (MBA) from Santa Clara University.
