Low-Cost F-to-V Converter Delivers Robust, Accurate Performance

Aug. 27, 2009
Although special-purpose frequency-to-voltage chips help you to create an F-to-V circuit block easily, they suffer from a major drawback. For given external components, their gainconstant, and hence voltage output, can vary more than ±5% from

Although special-purpose frequency-to-voltage chips help you to create an F-to-V circuit block easily, they suffer from a major drawback. For given external components, their gainconstant, and hence voltage output, can vary more than ±5% from piece to piece (e.g, the LM331 and the LM2917). Their currentsource value also varies piece to piece by a similar amount, thus causing piece-to-piece variations in the maximum voltage-output beyond which F-to-V goes into saturation.

This creates problems for mass-produced solutions requiring F-to-V conversion if the application can’t tolerate these variations. The result is messy trimming procedures for external passive timing components for each mass-produced piece.

This is where old workhorse LM555 outshines these special-purpose ICs. The 555 generates a mono-shot time-period equation:

TD (mono-shot delay) = 1.1 × RC

Timing accuracy is typically 1%. (For National Semiconductor’s LM555 and LM55C, it’s 0.5% and 1%, respectively.) Thus, designers can use timing components with precision tolerance to meet an application’s requirements, without unduly worrying about pieceto- piece chip variations.

A mono-shot-based F-to-V works by converting incoming pulses to a fixed-pulse-width, variable-frequency pulse-width-modulation (PWM) signal. The duration of the pulse is fixed at the period of the mono-shot (1.1RC in this case). This duration also forms the on period or duty-cycle of the PWM output.

Lower-frequency signals yield lower-percentage duty cycles, since the period forms a lesser percentage of the total period of the incoming pulse train. As the frequency rises, the output’s duty cycle increases, since the “on-period” is now a greater percentage of the incoming pulse-train period (Fig. 1).

This dc value of the output PWM signal (given by percentage duty cycle) is directly proportional to the incoming pulse-train frequency. However, the situation gets a bit tricky when the incoming pulse train has a period shorter than the on-period. The F-to-V is now supposed to saturate to its maximum value for all of the frequencies with time periods less than the mono-shot on-period.

However, if the mono-shot is not re-triggerable, it will expire “asynchronously” with the incoming pulse triggers, causing random output variations. As a result, the example circuit uses a transistorized discharge-switch to allow the 555 to re-trigger, which it otherwise could not do (Fig. 2).

Transistor Q1 forms a discharge path around capacitor C2. Resistor R4 and capacitor C2 are the timing components of the mono-shot with a time period of about 0.39 ms. Hence for a frequency of about 1 kHz, the output duty cycle is 39%, giving a voltage of about 4.68 V for a VBATT of 12 V. C1, R1, D1, R2, and R3 form the base trigger circuit for Q1. The 555’s internal transistor at pin-7 is not unused in this circuit. Rather than leaving the pin un-terminated, R5 and C3 terminate it as recommended by some CMOS 555 chip vendors. It can also be used as an auxiliary source of a sawtooth wave if required by the application. R6 and C5 form an output low-pass filter to extract dc voltage from the PWM pulse-train appearing at the IC’s pin 3.

The circuit’s output voltage increases linearly at the rate 4.68 V/kHz up to 2.5 kHz (Fig. 3). The output then saturates to its maximum value as desired (as a consequence of the re-triggerable feature of this mono-shot circuit).

About the Author

Staff

Articles, galleries, and recent work by members of Electronic Design's editorial staff.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!