Two major semiconductor players have unwrapped plans to ramp up production in the 0.13-µm (130-nm) CMOS process. Combining innovations in copper wiring, silicon-on-insulator (SOI) transistors, and improved low-k dielectric insulation, IBM will begin manufacturing for external customers this year. Meanwhile, Intel is migrating to the 0.13-µm CMOS process for achieving speeds beyond 2 GHz for future Pentium lines.
Intel says it will begin producing its 130-nm CMOS process on 200-mm wafers this year. Slowly, the company will migrate to 300-mm wafers next year. In its 130-nm process, Intel has reported 70-nm gate lengths and 1.5-nm gate oxide thicknesses (see the figure). The 130-nm process features six layers of dual damascene copper interconnects while using a high aspect ratio (thickness/width) of 1.6:1 to obtain high circuit density and lower line resistance simultaneously. These ultra-small transistor features were demonstrated using normal deep-ultraviolet lithography tools.
The manufacturer's researchers also have made strides in further scaling the transistor size down to 30 nm with a gate-oxide thickness of only three atomic layers. As a result of this breakthrough, Intel will be able to build microprocessors containing 400 million transistors, running at 10-GHz speeds and operating at less than 1 V, within the next five to 10 years.
"As our researchers venture into uncharted areas beyond the previously expected limits of scaling silicon, they find Moore's law still intact," says Sunlin Chou, vice president and general manager of Intel's Technology and Manufacturing Group. In scaling the device size to a new low, Intel's researchers have addressed the electrical leakage problem that has been a barrier.
"Our research proves that these small transistors behave in the same way as today's devices, thereby ensuring that there are no fundamental barriers to producing these devices in high volume in the future," notes Gerald Marcyk, director of Intel's Components Research Lab, Technology and Manufacturing Group.
Unlike Intel, IBM's 130-nm SOI process implements up to nine layers of copper wiring. Labeled CMOS 9S, it employs the SiLk dielectric with a k value of 2.7. This technology will be used to produce high-performance microprocessors with clocking speeds over 2 GHz and high-density, high-speed SRAMs as well.
IBM's Semiconductor Research and Development Center, East Fishkill, N.Y., will serve as a pilot production line for CMOS 9S. The company then will move the 0.13-µm process to its high-volume Burlington, Vt., facility this year.
This process was developed jointly with Infineon Technologies AG of Germany and foundry service provider United Microelectronics Corp. (UMC) of Taiwan. Infineon and UMC also are designing and building chips with the 0.13-µm CMOS process. Next, the three firms plan to move toward 0.1-µm feature sizes.
For more information on the IBM process, go to www.chips.ibm.com. For information on Intel's process, visit www.intel.com. And, see www.umc.com and www.infineon.com for additional details about the partnership.
