No, not yet. But it can’t go on forever. The number of transistors on a chip has doubled about every two years for almost five decades. Smaller transistors can fit into smaller spaces, making it possible to put more circuitry on the same size or a smaller chip. We also have seen higher digital speeds, high-frequency RF circuitry, lower power consumption, and lower costs. But as devices get smaller, we approach the atomic level of the materials, meaning the downward scaling will come to an end.
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Adam Brand and Gigi Lai of Applied Materials say that Moore’s law will continue, at least for now. Scaling to smaller transistor geometries will not be as easy, though. CMOS scaled nicely down to about 28 nm but smaller sizes have presented leakage, materials issues, and limits in the processing equipment. Right now we are at the 22-nm node with 14 nm in the wings. Some companies are even working on the 7-nm node and perhaps one or two more nodes at 5 nm or 3.5 nm are possible, but not without some major changes.
New architectures and geometries have emerged in response. The new circuitry is more 3D or vertical. Imec’s smaller FinFET design enables CMOS at the 22-nm level. Also, indium gallium arsenide (InGaAs) or indium phosphide (InP) can be used with the silicon to make the transistor faster and smaller. IBM is exploring the use of InGaAs with silicon germanium (SiGe) to produce smaller and faster CMOS devices. Chip-stacking techniques offer some promise as well. Such techniques could help scale CMOS down to the 7-nm node. Are you ready for 0.5-V dc supply voltages and 200- to 300-mV thresholds?
But that’s not all. New processes are also necessary. To date, the biggest factor in limiting the downward scaling has been the photolithography process that translates the design patterns into the masks that are used in deposition and etching. Immersion lithography and double patterning have helped, but the ultimate solution appears to be extreme ultraviolet (EUV) lithography. EUV has been in the works for years and is still not ready. It is expected to be available in 2015 and beyond.
Another development is the trend to 450-mm wafers from the current 300-mm size. This will offer pricing advantages, like the 200-mm to 300-mm wafer transition did. But the transition to 450-mm wafers will require all new fab tools, which is expensive. The way things are going, you may not see 450 mm until 2018 or beyond.
For many years the processors and memory chip businesses have driven Moore’s law. Today, the mobile and wireless business is driving the need for faster and smaller chips that consume less power. That trend will continue to rely on Moore’s law.
The continuation of Moore’s law is possible, but it will be more complex and more expensive. We might see the traditional two-year interval extend to three years to enable the industry to develop more complex materials, processes, and equipment. The costs will be excessive, creating an economic slowdown as well. Costs are already making Intel delay its 14-nm fab in Chandler, Ariz., because of low PC processor sales. Yet there is both hope and an agenda as the industry works to keep the good times going.