Compared with existing NPT technology for IGBTs, SPT reduces on-state losses by 20% and switching losses by 20% - without increasing thermal resistance.
When asked for their wish list for future insulated gate bipolar transistor (IGBT) modules, users in the mainstream industrial drives and light traction application areas requested some very challenging characteristics. For example, they were looking for more compact packaging, mechanical integration into the system, and fast and easy assembly.
From the IGBT and diode side, users asked for low losses, soft EMC-friendly switching waveforms, low thermal resistance and easy drive. Commercially, multiple sourcing and system cost were obviously important, but the ability to cover a wide power and voltage range with as few part numbers as possible also brings major logistical benefits. Furthermore, reliability and a predictable product lifetime were key factors. This wish list was the design goal for LoPak packaging (see Photo 1) and Soft Punch Through (SPT) IGBTs.
Punching Through Softly To understand the operation of SPT IGBTs, we must first look at the Punch Through (PT) and non-punch through (NPT) IGBTs. PT employs relatively thick IGBT chips made from epitaxial wafers and contains an N+ buffer (or Field Stop) layer. NPT types use thinner chips made from lower cost float zone (FZ) wafers that don't have the additional N+ layer.
You can see the differences between the performance of these technologies highlighted in Fig. 1, on page 32. One reason for the growth in the popularity of NPT is that the cost of its FZ wafers is significantly lower than that of the PT type (epitaxial wafers). When planning the introduction of a new SPT 1200V generation, it was very important to select the best parameters from each of the PT and NPT technologies and to combine them in one new device. It was equally important to ensure that this combination could be achieved using the lower cost FZ wafers.
SPT On-State Characteristics Fig. 2(a), on page 32, shows the on-state characteristic of an SPT 100A, 1200V die. The values achieved are a 20% reduction, compared to the existing NPT product. The SPT range has no increase in thermal resistance compared with the existing NPT generation, which leads to the SPT's significant increase in usable current in a real application.
The curves in Fig. 2(b) show SPT dies have a relatively resistive on-state characteristic. This makes the nominal current value of VsubscriptCE(SAT) all the more remarkable, because the device on-state voltage at low collector currents is even more competitive than the datasheet nominal current value. This low on-state voltage at low collector current means that during the low current part of the current sinewave generated in an inverter, the on-state losses are even lower than would be expected by simply considering the nominal current value.
SPTs were designed for application in the LoPak range of industry standard modules. One of the key features of these modules is parallelability. For example, you can use a 300A, LoPak5 6-pack as a 900A, 2-pack by connecting the module phase connections in parallel. The resistive on-state characteristic has major advantages in this area as well. SPT dies are not particle irradiated for carrier lifetime killing. This makes the spread of characteristics very narrow, so any mismatch in voltage drop across dies at a given current is transformed into a mismatch, or uneven sharing, of collector current. The slope of the V subscript CE(SAT) vs. I subscript C curve defines the extent of the current mis-sharing for a given mismatch in on-state between the two chips. In this way, the resistive SPT characteristic is well suited to parallel connection in contrast to "flat" diode-like characteristics demonstrated by many other IGBT types.
The well-known NPT-like positive temperature coefficient of on-state voltage is also important for paralleling SPT dies. In this respect, the negative feedback effect of temperature on the SPT's on-state voltage is the same as the NPT characteristic.
In many application areas (motor braking or low motor speed) diode current sharing can be more critical than IGBT sharing. The 1200V MPS diodes used in the LoPak series also have a positive temperature coefficient - improving not only IGBT, but also diode current sharing as you can see in Fig. 2(b).
As modules become more compact and the on-state voltage of the die reduces, the internal connection resistance of the module itself becomes increasingly important as a proportion of the total module, on-state voltage drop. This internal resistance has recently been given the symbol R subscript CC-EE. The SPT die line-up has an open emitter surface and corner gate, so almost the complete emitter area of the chip is available for bonding during module construction. This has a number of benefits in terms of the flexibility of module construction. However, in terms of module internal resistance, it allows you to use a larger number of bond wires per die than before, resulting in a lower value of R subscript CC-EE (see Photo 2, on page 34).
Soft Switching Edges Waveforms in Fig. 3, on page 34, compare NPT and SPT devices being switched under the same conditions. Here, the collector emitter voltage rise of both devices is almost identical, so the dV/dt seen at the inverter output and across the gate drive isolation barriers remains the same. The voltage overshoot seen by the system using SPT is reduced. This allows more margins on reverse bias safe operating areas (RBSOA), and doesn't require such a low inductance dc link - which gives the system designer more bus bar design freedom. You can see turn-off energy losses for an SPT LoPak5 in Fig.4.
The slope of the collector current fall in NPT and SPT is almost the same; however, the current tail of the SPT is much shorter and therefore generates 20% less turn-off switching loss. In addition, the uniquely soft transition from current-fall to current-tail of the SPT makes them EMC friendly.
In this way, SPT breaks through the old trade-off between switching losses and EMC compliance: 20% lower switching losses and EMC compliance - rather than 20% more losses to achieve compliance.
An SPT die is just as rugged as the well-known NPT technology. There's no need for additional costly or complex control circuitry to be built into the module to achieve the necessary ruggedness. Fig. 5 illustrates the RBSOA conditions of a LoPak5 switching off 600A at 900Vdc and generating a 1200V peak.
Waveforms in Figs. 6(a) and (b) show the 300A, 1200V LoPak5 device on a 900Vdc link in short circuit with small series inductance and with significant load inductance, respectively. The first waveform is representative of the case when one IGBT element in a phase leg fails or when there is a malfunction in the gating/control circuitry so that both devices in a leg are switched on simultaneously. Practically, the short circuit with some load inductance [Fig. 8(b)] is more likely to happen in a real application.
Unfortunately, this is usually also the more severe case. The short circuit current rise is limited by the load inductance until the IGBT begins to come out of saturation. As the voltage across the IGBT begins to rise, charge is pumped through the reverse transfer (or Miller) capacitance of the device and begins to lift the gate voltage above the normal 15V level. The waveform shows that the gate reaches around 17V in this case, although internally on the IGBT side of the internal sharing resistors and gate inductance, it's likely to be higher. The increased gate voltage drives the IGBT on harder, further increasing the short circuit current. The cell design of the IGBT allows an exceptionally high ratio of input-to-reverse transfer capacitance, so that this IGBT is particularly insensitive to this effect and therefore easier to use in this critical short circuit mode.
The rugged short circuit and the SOA capability of the SPT die is intrinsic to the IGBT design itself and is not achieved by adding extra control circuitry inside the module. This keeps module cost down and means system manufacturers do not need additional components or cost in their assemblies.
Gate drive requirements for the SPT are the same as existing NPT devices. For example, a 100A, 1200V SPT die needs only 1 mC of gate charge to switch 600V with a gate voltage of 0V to `15V. Even switching from a 115V gate supply, only 1.5 mC is required. As you can see in Fig. 7, on page 36, a driver with a pulse current capability of only 1A is sufficient to drive the 100A device at reasonable speed. This means you can implement the SPT into a design quickly - without the need for redesigning existing gate drives. Fig. 7 shows the typical gate characteristics when switching for the 100A, 1200V LoPak3 six-pack. SPT's characteristics allow the design of inverters using only three LoPak modules for drives in the 40kVA to multi-MW range.
Often, you determine the size of an inverter by the amount of power it needs to dissipate from internal losses to the air or other cooling system - without generating internal over-temperatures. We have already seen that the SPT IGBT generates very low losses; however, this alone is not enough to ensure an efficient compact and reliable system. Another important factor is thermal resistance. For given losses, you can keep the IGBT junction below the necessary limits, only by an appropriate thermal resistance. This thermal resistance is the sum of the heat sink-to-air and that internal to the IGBT module (junction-to-case) plus any contact thermal resistance. It follows then that generally the lower the module thermal resistance, the smaller the heat sink can be and the more compact the inverter can be.
By avoiding relatively expensive trench technology, we can afford to put more silicon into the same current rating of a chip and therefore achieve a much better value of thermal resistance than smaller trench chips.
Referring back to the original wish list, the SPT IGBT meets most of its targets. SPT combines the losses of a trench device with the thermal resistance, ruggedness and simplicity of a planar gate IGBT. Both switching and on-state losses are reduced by 20% compared with current NPT devices. Because thermal resistance is not increased, the SPT offers more actual usable current per rated amp, so that system designers can make equipment smaller and more cost-effective than ever before.
The unique blend of PT and NPT technologies used to generate the SPT design results in a device with an almost perfect soft turn-off waveform, making EMC compliance easier. The short low current tail not only leads to 20% lower switching losses than the current NPT product, but also to reduced over-voltage during switching.
LoPak Packaging SPT technology is now being introduced into LoPak packaging. LoPak3 is already available with NPT technology and is compatible with the industry standard 75A and 100A, 1200V Econopack modules. However, the main packaging focus here is on the new industry standard LoPak4 and LoPak5 packages.
Based on the design targets identified earlier, the first step in developing LoPak4 and LoPak5 was to decide on the correct topology for the LoPak range. The following were the primary considerations:
- Minimum number of part numbers for customer to qualify, purchase to cover maximum number of applications in 40kVA to multi-MVA inverter range,
- Minimum number of packages to develop, tool, manufacture and qualify for suppliers,
- Packaging should be as integrated as possible without compromising standardization,
- Compact and mechanically integrated into system,
- Extremely easy to assemble into system, with relatively easy disassembly, and
- One packaging platform to address industrial and traction sectors.
Fig. 8 shows the options considered for LoPak topology: 1-packs, 2-packs, 6-packs, Intelligent 6-packs, Application Specific Intelligent. Here, you can use the 6-pack (or more precisely, three 2-packs in one package) as a 2-pack with three times the current rating. This means that fewer packages are needed to cover a whole line-up of systems. For example, you can use the 300A LoPak5 in a 300A application. However, by parallel connecting the phase terminals, the same module can fulfil a 900A application.
Fig. 9 shows how (with only the 1200V LoPak4 and LoPak5 ratings) a whole power range of inverters can be built in 400Vac to 500Vac ratings.
One of the main aims of the LoPak4 and LoPak5 packages is to minimize system size and assembly time. The devices themselves are extremely compact. However, due to the high level of mechanical integration, it's possible to manufacture an inverter where all components (excluding heat sink and link capacitors) fit within the module envelope.
Power connections to the module have been inverted, compared with a traditional standard module. Rather than a nut into which the user screws a bolt to locate the bus bar, a bolt is provided as the module power terminal. One of its two major advantages is that it's possible to achieve a much lower profile module, as the height needed by the bolt entering the module can be subtracted from the module height. This means that the equipment can be more compact and more importantly, the actual connection to the chips from the bus bar is significantly shorter than in the case of the higher standard modules, leading to lower inductance in the power circuit.
The bolt connection also allows a pre-built laminated bus bar to be located onto the terminals during inverter assembly. By contrast, the assembly with traditional nut connections requires the bus bars to be held in place until at least two bolts have been screwed into the module.
Modules are designed to take a p. c. board containing control and gate drive, which snaps on to the module, and is held in place by rugged hooks. Figs. 10 and 11 show the construction details. The use of spring contacts eliminates the difficult process of soldering to a big module and produces a more reliable contact.
The spring contact also allows you to remove the p. c. board, should it need servicing. A low-profile channel runs along the center of the module's long dimension, to allow for high board-mounted components, like capacitors and magnetics.
Auxiliary connections are located as close as possible to the chips inside the module. This avoids unnecessary tracking inside the module, which would make it larger and therefore more costly than necessary. The user has the opportunity to place the low-impedance gate circuit loops of the drive circuit close to these pins, minimizing the inductance between the real driver and the chips themselves. In this way, the user can achieve gate circuitry with high noise immunity and optimize the switching of the device to the application.
Qualification Philosophy Methodology to demonstrate component reliability can be divided into standard reliability tests (e.g. high temperature reverse bias testing) and tests where wear-out failure is expected to be the decisive factor in system lifetime (e.g. power cycling testing).
For wear-out mechanisms failure probability rates of 1% rather than the median life values (50%) are important for system reliability considerations, particularly in systems containing a large number of non-redundant IGBT modules. For example, 50% module failure probability information will only give a system manufacturer information about where his system is almost sure to fail. Conversely, even systems using several modules would have relatively low failure rates under conditions specified for 1% module failure (a system with 12 modules would only have around a 10% failure rate under those conditions).
Consider that the relevant lifetime parameter to study is the number of cycles to failure N subscript f, which by its very nature is a random variable. If we wish to analyze this random variable, we have to generate a certain number of failures (using a well-defined failure criterion) and then try to estimate the type and parameters of an applicable statistical distribution law. In our company, the generation of five failures through "end-of-life" tests is the minimum requirement, of course taking into consideration duration and cost of testing. It turns out that a Weibull type distribution law in most cases fits very well with the observations.
By knowing the lifetime distribution one may calculate the number of cycles to a predefined probability of failure e (the so-called e-percentile). In this case, we chose e40.01, because from a system point of view a 1% probability of failure on component level would result in 10% probability of failure on system level (assuming on average that a system would contain 12 such components in operation at any one time). In addition, more than 1% failures under normal operation would certainly indicate the beginning of the long-term wear-out phase.
LoPak3 Power Cycling tests You can address the complete LoPak qualification program with power cycling tests to demonstrate a practical example of reliability. End-of-life power cycling tests at DT subscript j480C have been performed for the baseless version of LoPak3, which uses an Al subscript 2O subscript 3 substrate material. The test conditions are listed in Table 1.
Five samples were tested into failure (DVce.10% or DRth.20%) with the results in Table 2.
You can see that the failures all occurred in a very narrow time interval. Fitting the measurement data with Weibull statistics (Fig. 12) allows predicting the failure percentile as a function of test time.
The scale parameter of the Weibull distribution (characteristic lifetime) at which the cumulated failure percentage has reached 63% (40.63 percentile) is at 79.4 kcycles. The shape parameter of the Weibull distribution is b445. This high value of the shape parameter is an indication of a mature technology and well-controlled manufacturing processes and materials. For this reason, the point at which the cumulated failure percentage has reached 1% (40.01 percentile) is with 71.7 kcycles only slightly lower than the characteristic life.
All failures that were encountered in the DT subscript j480C test were analyzed to understand the responsible failure mechanism. In all cases, solder fatigue between the die and the substrate was the root cause of the failure (Photo 3, on page 46). The presence of only one failure mechanism is a justification for fact that all failures have been modeled with the same failure statistic.
An extensive program of reliability testing is proceeding on LoPak4 and LoPak5. The vibration testing on LoPak4 (Photo 4) serves to illustrate the validation process for some of the more novel aspects of the design.
During the test, the gate driver board was mounted and the continuity of the auxiliary contacts was continuously monitored to ensure that - even under severe vibration conditions - good contact to the gate connections was maintained.
References 1. E. Herr et al., "LoPak IGBT Modules - Inverter Reliability Benefits," PCIM Boston (2000).
2. S. Dewar et al., "Soft Punch Through (SPT) - Setting new Standards in 1200V IGBT," Proc. PCIM Nuremberg (2000).
3. S. Dewar et al., "The Standard Module of the 21st Century," Proc. PCIM Nuremberg (1999).
4. G. Debled et al., "New Low Loss, Low profile IGBT modules for compact and modular inverter line-up," Proc. PCIM Chicago (1999)
5. K. Backhaus, "Performance of New Compact Power Semiconductor Module Families featuring Pressure Contact Technologies," Proc. PCIM Chicago (1999).
6. N. Kaminski et al., "1200V Merged PIN Schottky Diode with Soft Recovery," Proc. EPE Lausanne (1999).