Optimized PFC Controller IC Adheres to Harmonic Specs

A new European regulatory environment IEC 1000-3-2 lowers harmonic current emissions for all equipment drawing more than 75W from the ac line — which includes a high percentage of today's power supplies. A change in equipment classification designates consumer electronic equipment as Class D, which makes compliance more difficult to achieve. Although the IEC 1000-3-2 doesn't specify power factor correction (PFC) requirements, the easiest path to compliance standards is through a PFC front end.

A PFC front end, implemented with active or passive elements, results in a resistor emulation circuit — which allows the input current to track the input voltage sinusoid, achieving unity PF and low harmonic current distortion. Passive approaches involve bulky inductors and capacitors that can't be optimized for a range of operating conditions, limiting their use to a few cost-sensitive applications.

Active PFC circuits are implemented in many flavors, each seeking the dual goal of low implementation costs and acceptable overall performance. One of the earliest favorite topologies for active PFC is the continuous conduction mode (CCM) boost converter with average current mode (ACM) control. Other topologies such as DCM flyback, DCM boost, boundary-mode boost, and SEPIC have also been implemented in some applications. More recently, the trend is working toward topologies providing single-stage power conversion with PFC built in. While these alternatives have been explored in pursuit of the least expensive PFC solution, the CCM boost converter has held its own as the first choice for PFC implementation.

Basic PFC

Fig. 1 shows a simplified representation of the key power stage and control elements of a CCM boost converter with ACM control. This power stage has well-defined requirements for key components, such as the power switch Q1, rectifier diode D1, and power inductor L_IN. An inductor in the input path offers a means of shaping the input current as desired. You can use the input voltage waveform (represented as I_AC) as a reference to shape the input current waveform. Concurrent with the input current shaping, the converter also needs to regulate the output voltage. A multiplier is used in the control circuit to generate a single control parameter (switch duty cycle) from multiple inputs.

In its most basic form, the multiplier combines the output voltage error signal (V_AOUT) generated by the voltage loop and input voltage information represented by I_AC. The output of the multiplier is a current reference signal (I_MO) compared (after appropriate scaling) against the inductor current I_IN measured by the R_SENSE resistor. The inner loop, consisting of the current error amplifier and PWM comparator, ensures the inductor current follows the commanded value. The outer voltage loop regulates the output with a bandwidth less than one half the line frequency. If the voltage loop had higher bandwidth, it would interfere with the current loop and cause distortion in line current.

A closer look at the two-input multiplier reveals an inherent limitation when the input voltage (V_IN) changes. The waveforms in Fig. 2 illustrate this best. Fig. 2(a) and (b) show the input voltage and current waveforms for V_IN of 120Vac and 240Vac, respectively. As shown, when V_IN doubles, the input current (I_IN) has to halve to maintain constant power to the load. Fig. 3(a) and (b) show both multiplier inputs for these conditions. The I_AC input follows the V_IN and doubles. Since the multiplier output (I_MO) corresponds to the input current, it has to halve, which can only be accomplished by reducing V_AOUT by a factor of four.

Many of the designs have a universal input voltage range of more than 3-to-1 (85Vac to 270Vac) and the basic multiplier taxes the voltage amplifier range. Additionally, the peak power capability and the loop gain vary with the line voltage, compromising the ability to limit power and compensate the loop effectively. You can address these problems with a modified multiplier that has input voltage feedforward (V_FF) ^[1]. An appropriately scaled inverse squared rms value of the input voltage (1/V_FF²) is added as an input to the multiplier. With this term, the input voltage changes do not warrant a change in V_AOUT for a given load. In fact, the voltage amplifier output becomes proportional to the output power for the normal operating range. To illustrate this, revisit the example given in Fig. 2 and 3, on page 27. When V_IN doubles, the new input (1/V_FF²) reduces by a factor of four, and coupled with a doubled I_AC, results in the desired value of half the original I_MO without any change in V_AOUT. An advantage of this technique is constant loop gain and peak power over the input range.

Voltage feedforward adds implementation complexity (inside and outside the control IC), but can be simplified with new techniques. Traditional circuits used an external 2-pole filter to derive the V_FF, while keeping the ripple low. In new generation PFC controllers, such as the UCC3817, mirroring the I_AC current into a single-pole filter has simplified this. Adequate filtering is required as any second harmonic ripple on the V_FF input contributes to the third harmonic content on the input current.

Multiplier Characteristics

Equation (1) is the fundamental equation that governs the multiplier operation, relating the current output of the multiplier (I_MO) to the three inputs.

(1)
Where:

I_AC = Multiplier input current, proportional to instantaneous V_IN
V_AOUT = Output voltage error signal
V_FF = Average value of rectified line voltage
K = Multiplier gain

The (V_AOUT-1) term ensures that I_MO can go to zero easily at low power. The shape of the I_MO current is similar to I_AC and the rectified input voltage. For a given V_IN, the peak of I_MO is proportional to V_AOUT. The voltage loop must have a crossover frequency significantly below the line frequency to prevent V_AOUT from varying during a line cycle. Therefore, all inputs to the multiplier, other than the I_AC, should be constant during a line cycle.

Equation (1) assumes linear and idealized performance over the range of operation. However, IC implementations aren't ideal, and any nonlinearity can create distortions in I_MO (and consequently in I_IN). For example, if multiplier gain, K, is different for low and high values of I_AC, the I_MO shape won't be a faithful reproduction of the line voltage shape. Since I_MO is the reference signal for input current, its dependencies on parameter variations need to be characterized carefully.

You can explore further effects of the multiplier on system operation with the help of multipliyer operation curves shown in Figs. 4 and 5, on page 32. Fig. 4 shows the peak multiplier output current (I_MO-PK) vs. V_AOUT for fixed line voltage (V_IN and V_FF). The actual I_MO varies between 0 and I_MO-PK proportionally to the I_AC during a line cycle. Adjusting V_AOUT through the outer loop can compensate any multiplier nonidealities in the middle portion of the curve. For example, if the I_MO isn't adequate at a given condition, V_O will drop, V_AOUT will increase, and I_MO will adjust.

At low power operation, V_AOUT approaches the lower end of its operating range (1V) and commands zero I_MO at no load through Equation (1). If there's residual (non-zero) I_MO at this point, some power will be delivered to the load. In the extreme case, this can lead to overvoltage on the output and trigger the overvoltage protection (OVP) circuit in the system. The consequences of reaching OVP include higher stress on the devices and controller biasing (Vcc) problems. During the OVP condition, switching is stopped and the self-bias circuit used in many systems (a winding off the boost inductor) loses its energy source. The controller Vcc can fall below the undervoltage lockout (UVLO) turn-off threshold during this condition and lead to a hiccup operation mode.

To prevent this effect, minimize the residual I_MO and specify it in the data sheet. You can also provide an alternate path to limit switching. Once V_AOUT falls below a set threshold (e.g. 0.33V), it can be interpreted as zero power command and a direct signal to the output to stop switching. This zero power detect (ZPD) technique, incorporated in the new generation PFC controllers, prevents an overvoltage condition and potentially prevents the bias problems described above.

The ZPD technique allows a more natural design of the current error amplifier, showing that positive current amplifier input offset voltage could result in power delivery under no load condition (same effect as described above). Some controllers intentionally skew the offset in the opposite direction to negate this effect. However, that results in a distortion near every zero crossing (due to the artificial offset) and nonideal current amplifier design. With the ZPD technique, designers can develop the current amplifier for near-zero offset, assuring adaquate handling of the low power mode.

Despite the useful ZPD technique, a proper multiplier design should allow as wide a load range as possible (>20-to-1) — without giving up control to the ZPD path. It's important to specify the multiplier performance at the corners of V_AOUT. For example, a specification range of V_AOUT =1.25V to V_AOUT=5.5V designates an 18-to-1 load range (factoring in the 1V offset in the multiplier). Of course, as V_AOUT gets closer to 1V, some nonlinearities start creeping into the multiplier operation, and it's harder to specify limits in a spec table. A characteristic curve similar to Fig. 4, on page 32, can help.

Fig. 5, on page 32, shows the product of V_FF and I_MO-PK (a quantity representative of input power as V_FF and I_MO-PK are proportional to V_IN-RMS and I_IN(PK/RMS), respectively) as a function of V_FF (representative of V_IN-RMS) for a fixed value of V_AOUT. You can view the curve as representing the maximum V_AOUT (full load) condition. As depicted, there are two distinct regions of operation. The first region, labeled constant power region, is the area where the multiplier operates over nominal line range. Referring to Equation (1) and rearranging terms, you can see the I_MO-PK × V_FF term will be constant over the V_IN range for a given V_AOUT. This is because I_AC-PK and V_FF vary proportionally. This curve shows the benefits of the voltage feedforward scheme.

Because of V_FF, the V_AOUT remains constant for a given load as line voltage varies. It also ensures that the peak system power delivered will be constant over the V_IN operating range. The second region, labeled power limiting region, protects the converter under line dropout or brownout situations. The multiplier output is systematically limited in this region so the input currents are contained and power stage components are protected from overheating at low-line operation. In many PFC controllers, this characteristic is achieved by limiting the I_MO to a maximum of two times I_AC. In this region, the output power requirements aren't met and output voltage starts dropping [2].

Fig. 5 also depicts the potential deviations from ideal of the constant power curve due to multiplier nonlinearities. A lower-than-expected value means the peak power delivered at high line is lower than the power delivered at low line. In that case, the system design must accommodate full-load operation at high line with correspondingly higher dissipation at low line.

Other Features

Traditional PWM controllers use a trailing edge PWM scheme, where the output is turned on at the start of the switching cycle and turned off during the switching cycle when the PWM ramp crosses the error voltage. Leading edge PWM, an alternative scheme, is more appropriate for the PFC controllers, because the output is turned off at the beginning of the switching cycle and turned on when the PWM ramp crosses the error voltage. Another inversion is added in the feedback path (in the current error amplifier, in these new PFC controllers), to maintain overall negative feedback. When synchronized with a downstream converter that is trailing edge modulated, the leading edge PWM can result in a substantial reduction in boost capacitor current ripple ^[3]. Depending on the application, this can lead to a smaller/cheaper boost capacitor or increased reliability from the same capacitor.

When specifying and evaluating PFC controllers, reference voltage accuracy is critical. At first glance, it may appear that the PFC output doesn't need to be tightly regulated, therefore there's no need for a tightly regulated reference. However, a careful analysis reveals the opposite picture, as illustrated in Fig. 6. The PFC output must be between two predetermined voltages at any instance. The peak of the maximum ac line voltage and the minimum duty cycle of the controller set the lower limit. The boost converter conversion ratio dictates this constraint:

V_o = V_IN/(1-D).

For 265Vac input and 3% controllable duty cycle, this voltage is 386V (V_OMIN). The voltage rating of the boost capacitor (typically 450V) constrains the maximum PFC voltage. Also, any PFC output has a 2X-line frequency ripple determined by the output capacitance and the power level. If 1 μF of capacitance is used for every watt of output power, this ripple (V_RIP) is 3.3V peak. As a result, you must set the minimum dc voltage at (V_OMIN + V_RIP). The output voltage tolerance is based on the V_REF tolerance (along with the divider resistor tolerances). As shown in Fig. 6, the OVP setting (its relation to the V_O setting and its own tolerance) will determine another band where the output can be during OVP conditions. Fig. 6 shows with a 1.5% tolerance on V_REF (and 1.675% on OVP setting), the derating or headroom available is only 21V. With a looser spec on the V_REF, this headroom reduces or disappears in some cases, causing severe reliability concerns.

References

1. “High Power Factor Preregulator for Off-Line Supplies,” L.H. Dixon, Unitrode Seminar SEM-600, 1988, reprinted in subsequent seminar manuals.

2. UC3854A/B and UC3855A/B provide power limiting with sinusoidal input current for PFC front ends (Texas Instruments Application Note SLUA196/DN-66).

3. “Practical Design Issues for PFC Circuits,” James P. Noon and Dhaval Dalal, APEC 1997, pp. 51-58.

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