DDR Memories Require Efficient Power Management

Now gaining popularity in desktop and portable computers is a new type of memory: Double Data Rate (DDR) memory that meets JEDEC Standard JESD79 and JESD8-9 ^[1]. The DDR-SDRAM is simple, clocked at the same speed as older SDRAM (synchronous dynamic random access memory), yet handles twice the amount of data by using the rising and falling edge of the clock signal for data transfers. DDR-SDRAM has another difference from the older memories: It requires 2.5V, instead of 3.3V used by the older SDRAM.

Compared with the older single data rate SDRAM, DDR-SDRAM exhibits superior performance: 266 MHz vs. 133 MHz data rate for older SDRAM. DDR-SDRAM has lower power dissipation — at a competitive cost. This and the lower capacitance inside the memory chips lead to a reduced power consumption, making DDR-SDRAM also attractive for notebooks. However, these faster DDR-SDRAM require a new and more complex power management architecture than the previous SDRAM technology.

Power Management

Fig. 1, on page 17, illustrates the basic power management architecture for DDR memories. It has a push-pull output buffer, while the input receiver is a differential stage requiring a reference bias midpoint, V_REF. Therefore, it requires an input voltage termination capable of sourcing as well as sinking current. This last feature differentiates the DDR termination voltage (V_TT) from other terminations present on the PC motherboard. That is, the termination for the Front System Bus (FSB), connecting the CPU to the Memory Channel Hub (MCH), which requires only sink capability due to its termination to the positive rail. Hence, such DDR V_TT termination can't re-use or adapt previous V_TT termination architectures and requires a new design.

Between any output buffer from the driving chipset and the corresponding input receiver on the memory module, you must terminate a routing trace or stub with resistors R_T and R_S (Fig. 1). Accounting for all the impedances, including the output buffer's, each terminated line can sink or source ±16.2mA (this is more than the older figure of ±15.2mA per the June 2000 Revision of JESD79)^[2]. For systems with longer trace lengths between transmitter and receiver, it may be necessary to terminate the line at both ends, which doubles the current.

The 2.5V supply (V_DDQ) required for the DDR logic has a tolerance of ±200mV. To maintain noise margins, DDR termination voltage, V_TT, must track V_DDQ. It must be equal to V_DDQ/2, or about 1.25V, with an accuracy of ±3%. Finally, the reference voltage, V_REF, must be equal to V_TT to ±40mV. These tracking requirements and the requirement that V_TT can sink and source current are features that present the unique challenges for powering DDR-SDRAM.

Peak and average current consumption for V_TT and V_DDQ are two parameters for the correct sizing of our power supply system. To find the peak power requirements for the termination voltage, we must determine the total lines in the memory system. A 128Mbyte memory system includes:

128-bit wide bus

8 data strobe bits

8 mask bits

8 Vcc bits

40 address lines (2 copies of 20 addresses)

Therefore, the total number of lines is 192.

Each line consumes 16.2mA, so that the peak current requirement is:

192 × 16.2mA=3.11A

V_DDQ sources current during the phase in which V_TT sinks current. It follows that this portion of the current for V_DDQ is unipolar and its maximum equals V_TT's maximum value of 3.11A.

A 128 Mbyte memory system usually consists of 8 × 128Mbit devices and consumes an average power of 990mW, excluding the V_TT termination power ^[3]. It follows that the average current, I_DDQ, drawn from V_DDQ is:

I_DDQ=P_DDQ/V_DDQ
(1)

Where:

I_DDQ=Average current

P_DDQ=Average power, excluding V_TT termination power

V_DDQ=Supply voltage

I_DDQ=990mW/2.5V=0.396A

Similarly, the average power, P_TT, consumed by the termination resistors is 660mW ^[1]. It follows that the current I_TT drawn from V_TT is:

I_TT=P_TT/V_TT
(2)

Where:

I_TT=Current drawn from V_TT

V_TT=Termination voltage=1.25V

P_TT=Average power

I_TT=660mW/1.25V=0.528A

Finally, select the V_REF current, I_REF, with a value high enough for the V_REF supply to exhibit low enough impedance to yield noise immunity (<5mA).

Naturally, if V_DDQ also powers other loads besides the termination load then its sizing must increase accordingly.

Transient Operation

The governing documents for DDR memory, JEDEC JESD79 and JESD 8-9, specify the V_TT voltage must be equal to half the V_DDQ voltage with a tolerance of ±3%. This tolerance should include busload transients caused by transitioning lines. However, two items necessary for evaluating the capacitor requirements for the V_TT supply are missing from the JEDEC spec: it doesn't specify the bandwidth over which V_TT must track V_DDQ, nor does it specify V_TT's maximum load transient.

In practice, the intent of the spec was to maximize noise margins. Thus, while it's not mandatory for V_TT to follow half of V_DDQ at all times, the greater the bandwidth with which it does so, the more robust the system. For this reason, a wide-bandwidth switching converter is desirable for generating V_TT.

For the V_TT load transient, the current could go from +3.11A to -3.11A, when going from sourcing to sinking current. This 6.22A step with a 40mV window would require an output capacitor with an ESR of only 7mΩ:

ESR=V_W/I_S
(3)

Where:

V_W=Voltage window (40mV)

I_S=Step current (6.2A)

ESR=40mV/6.22A=7mΩ

Two practical considerations moderate this requirement, however. The first is actual DDR memory doesn't really draw 3.11A — measurement shows typical current in the range of 0.5A. Second, the transition between sinking and sourcing current occurs quickly — so quickly the converter doesn't see it. To go from positive maximum current to negative maximum current requires the bus to go from all ones to all zeros and then remain in that state for a time at least equal to the inverse of the converter bandwidth. This is on the order of 10μsec. Since the bus runs at 100 MHz, it would need to stay at all zeros for 1000 cycles. Then, the output capacitor for V_TT needs about 40mΩ ESR:

ESR'=V_W/I_T

Where:

I_T=Typical step current (1A)

ESR'=40mV/1A=40mΩ

DDR memory supports standby operation. In this mode, the memory retains its contents, but is not actively addressed. For example, such a state may be seen in a notebook computer in standby mode. In standby, the memory chips do not communicate, and so you can turn off the V_TT bus power to save power. V_DDQ, of course, must remain on in order for the memory to retain its contents.

Linear vs. Switching

As noted earlier, the average power dissipation of a DDR system is:

P_DDQ=Average power, excluding V_TT termination power=990mW

P_TT=Termination power=660mW

For a total of:

P_TOTDDR=990mW + 660mW=1650mW

In contrast, a comparable SRAM system consumes 2040mW ^[3].

Using a linear regulator to terminate V_TT means the processing of P_TT power results in 50% efficiency, according to the ratio Vout/Vin=V_TT/V_DDQ=0.5. This means the V_TT regulator dissipates an additional 660mW, raising the total average power dissipation to 1650 + 660=2310mW. Such a figure now exceeds the corresponding power dissipation figure for older SDRAM, wiping out one of the advantages of the DDR memories, namely lower power dissipation.

As far as P_DDQ goes, most of the power advantage comes from having a V_DDQ of 2.5V, as opposed to 3.3V for conventional SDRAM. However, in a typical PC environment, the silver box provides the 3.3V, while the 2.5V is not available and must be created on the motherboard. Unless an efficient regulation scheme generates V_DDQ, the power dissipation advantage is once again lost. It follows that switching regulation should be the preferred means of processing P_DDQ and P_TT power for DDR memories.

Although there is a variety of DDR power ICs (the ML6553/4/5 with integrated MOSFETs, and the FAN5066 for high power systems), the FAN5236 (sampling now) is designed for all-in-one powering of DDR memory systems. Integrated in this single IC are a switcher controller for V_DDQ, one for V_TT, and a linear buffer for V_REF. The switcher for V_DDQ runs off any voltage from 5V to 24V. However, the switcher for V_TT is different: It runs from the 2.5V V_DDQ power, and switches synchronously with that switcher.

Since the bus lines are driven with 2.5V V_DDQ and are pulled up to 1.25V V_TT, the power circulates between V_TT and V_DDQ. Drawing V_TT from V_DDQ minimizes total circulating power, and thus circulating power losses. The V_TT switcher can also be shut down for standby mode. Fig. 2 shows the typical application.

Fig. 3 shows the basic block diagram for V_TT and V_DDQ. Intersil will also offer this function as ISL6225.

Future Trends

In the next few months, many new desktop computers will employ DDR memory — with notebooks only shortly behind. Customers will then demand more memory to run their larger software applications. To power this memory, the decreased power requirements of DDR may still not be adequate. For this reason, there's now work being done on specifications for DDR-II memory, which may be available in two or three years. DDR-II will likely reduce V_DDQ to 1.8V, with V_TT and V_REF reducing to 900mV.

References

JEDEC STANDARD JESD79, June 2000 and JESD8-9 of Sep.1998.
DDR SDRAM Signaling Design Notes; Micro Linear and Micron Technology; April 1999.
DDR DRAMS Pare Down Power for Laptop, Ling Ling Wang and Philip Leung of Acer Labs; Farhad Tabrizi of Hyundai Micro Electronics; July 2000; Portable By Design.

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