New Power MOSFET Package Allows Dual-Side Cooling

Feb. 1, 2002
A new patent-pending power packaging technology improves the thermal characteristics of surface-mount MOSFETs by allowing dual-side cooling (Fig. 1).

A new patent-pending power packaging technology improves the thermal characteristics of surface-mount MOSFETs by allowing dual-side cooling (Fig. 1). Designated the DirectFET, it doubles the system current density of high current dc-dc converters. This allows efficient top-side cooling with forced air or a thermally conductive gap-filling medium to conduct the heat to a suitable grounded heat sink.

Heat dissipation of next-generation, high-power microprocessors, combined with the heat generated in p. c. board traces carrying over 100A, bring the board temperature up to about 80°C — even before accounting for dc-dc converter heating. This leaves little room to dissipate the heat, without increasing the board space.

Improvements in silicon technology have reduced the die size and amount of heat generated by MOSFETs to the point where packaging is the performance limitation.

Besides their poor conductivity properties, SO-8 packages have poor thermal characteristics, aren't easy to heat sink, and can only effectively be cooled on one side. Poor thermal characteristics limit the current carrying capacity by restricting the amount of heat you can remove. For example, typical junction-to-p. c. board thermal resistance (Rqj-pcb) for an SO-8 is about 20°C/Wmax. A DirectFET package with the same footprint achieves less than 1°C/Wmax.

With a low die-free package resistance (DFPR), this packaging reduces the amount of heat generated by the device. Improved thermal resistance makes heat dissipation more effective.

Fig. 2 shows the DirectFET package. A copper housing contains the silicon die. The bottom of the package consists of a die specifically designed with source and gate contact pads that you can solder directly to the p. c. board. The copper “can” forms the drain connection from the other side of the die to the board. This package eliminates the conventional lead frame, wirebonds, and the plastic packaging limiting the thermal performance of most surface-mount devices. This technique minimizes the number of interfaces and the length of the conduction path, which reduces conduction losses.

Passivation of the silicon die isolates the gate and the source pads to prevent shorting, and acts as a solder mask when mounting the device on the p. c. board. The passivation layer also protects the termination and gate structures from moisture and other contaminants.

For electrical and thermal efficiency this configuration maximizes contact area between the source and gate pads and the board. Area contact pads are an electrical and thermal improvement over the multiple solder balls of BGA-type packages for power applications. These land grid array contacts are compatible with existing power board layouts that don't have the fine geometry control necessary for BGA-type packages. The copper can drain connection also provides an alternate path for heat dissipation and makes efficient use of a heat sink.

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