CSTBT Structure Outperforms Conventional IGBTs

Power semiconductor chip design involves a tradeoff between switching speed, static losses, safe operating area, and short-circuit withstanding capability. Historically, IGBT performance improvements evolved through finer surface patterns and shallow diffusion processing technologies. Recently, trench-gate cell structure and new carrier lifetime control processes produced significant performance improvements ^[2]. However, high cell density trench gate devices tend to have high short-circuit saturation currents. This characteristic degrades the short-circuit with standing capability of the device. In addition, the high cell density trench gate devices often exhibit significantly increased gate capacitance compared to their planargated predecessors. Their larger gate capacitance results in increased gate drive power requirements.

A recently introduced, improved 1200V IGBT overcomes the drawbacks of the conventional IGBT. The new device uses a chip structure called carrier stored trench bipolar transistor (CSTBT) to provide reduced on-state voltage compared with conventional IGBTs ^[1]. The CSTBT uses a light punch through (LPT) vertical structure to eliminate the need for epitaxial wafer material. It provides a positive temperature coefficient of V_CE(sat) for simplified parallel operation ^[3]. The new device is optimized for overall performance in industrial applications. The result is a novel Plugged Cell Merged (PCM) surface pattern that features low on-state voltage, improved short-circuit ruggedness and reduced drive power.

1200V CSTBT Concept

Fig. 1 shows an equivalent circuit model for an ideal IGBT in its on state. This circuit shows that the on-state voltage (V^CE(sat)) of an IGBT can be thought of as the sum of the forward voltage of a PIN diode and the R_DS(ON) drop of a MOSFET. Increasing the total channel width per unit chip area decreases the R_DS(ON) of the MOSFET portion of Fig. 1. High-density trench gate surface structures provide a substantial increase in channel width ^[2]. Also, the trench gate structure eliminates the parasitic JFET resistance associated with the MOSFET. As a result, you can link the largest component of on-state voltage in state-of-the-art 1200V trench gate IGBT devices to the forward voltage drop of the PIN diode portion of Fig. 1.

Normally, a PIN diode has a symmetrical excess carrier distribution in the n- region as shown by curve A in Fig. 2. Curve B shows that the excess carrier distribution in a conventional trench gate IGBT deviates from the ideal case by steadily decreasing as it approaches the emitter side of the device. This non-ideal behavior becomes even more pronounced in devices with high blocking voltage ratings. The decreased carrier concentration near the emitter side effectively increases the resistance of the PIN diode, which results in an increase in on-state voltage (V_CE(sat)).

A new chip design, the CSTBT improves the carrier concentration at the emitter side. The CSTBT has an additional n- buried layer. The buried layer provides “stored” carriers to produce the modified carrier distribution shown in curve C of Fig. 2. The resulting carrier distribution is closer to the ideal case and produces increased conductivity in the n- layer. The result is a substantial reduction in its on-state voltage. Fig. 3a and 3b show the cell structure of a conventional high cell density trench gate IGBT compared to the CSTBT. The key difference is the addition of the buried n- layer to provide increased carrier concentration near the emitter side of the device.

Besides the buried n- layer, the CSTBT chip utilizes an optimized vertical structure based on Mitsubishi's Light Punch-Through (LPT) technology. Fig. 4 shows a schematic comparison of conventional NPT, Epitaxial PT and LPT chips. The key to the LPT structure is an optimized n- drift region that it is thin enough to provide low V_CE(SAT) while maintaining a robust switching SOA. An n- buffer layer secures a sufficiently high breakdown voltage and low leakage current in the presence of the optimally thin n- drift region. The thickness of the n- drift layer is selected so that the depletion region extends to the collector when applying the rated voltage in the off-state. However, at normal operating voltages the depletion region does not reach the buffer layer, producing an operation characteristic similar to conventional NPT designs. Another feature of the LPT structure is optimized n+ buffer and p collector layers that provide controlled carrier concentration in the n- region during conduction. The result is efficient switching characteristics without the need for carrier lifetime control processing. The 1200V CSTBT chip fabrication is from low cost n- type single crystal (non-epitaxial) wafer material.

Fig. 5a shows a conventional high cell density trench gate IGBT. High cell density reduces V_CE(SAT) by making the R_DS(ON) of the MOSFET part of the device very low. Unfortunately, the MOSFET part of this structure also permits very high short-circuit currents, which degrades the short-circuit withstanding capability of the device. Under low impedance short-circuit conditions, the current becomes very high before the device desaturates and limits the current. The self-limited current of the IGBT is often called the short-circuit saturation current. As shown in Fig. 6 the short-circuit saturation current for the conventional narrow pitch trench gate IGBT with V_GE =15V is more than 15 times the nominal rated current of the device. This high short-circuit saturation current limits short-circuit withstanding capability of the chip alone to about 5µs. To recover the short-circuit withstanding capability required for many industrial applications, it is necessary to add an additional current limiting circuit to reduce the gate voltage under short-circuit conditions ^[2]. Unfortunately, this increases the complexity of the device. Obviously, it is desirable to have a chip with a lower short-circuit saturation current to eliminate the need for an additional current limiting circuit.

The short-circuit saturation current of an IGBT is primarily controlled by the characteristics of the MOSFET part of the device. One effective way to reduce the short-circuit saturation current and improve short-circuit ruggedness is to reduce the total channel width of the MOSFET part of the IGBT structure. This can be accomplished by using a wider cell pitch structure, as shown in Fig. 5c. Fig. 6 shows that the narrow cell pitch device has a short circuit saturation current of only about five times the device's nominal rating. Unfortunately, reducing the channel width of the conventional trench gate IGBT increases the R_DS(ON) of the MOSFET portion of the device, increasing V_CE(sat). Curves 5a and 5c in Fig. 7 show this undesirable increase in V_CE(sat).

You can use the CSTBT chip structure to mitigate the undesirable increase of on-state voltage caused by a wider cell pitch design. Shown in Fig. 5d is the structure of the wide cell pitch CSTBT. By selecting appropriate trench spacing and depth the series resistance and performance of the MOS and diode regions you can optimize the device to provide low on-state voltage while maintaining low short-circuit saturation current.

Fig. 6 shows the short-circuit saturation current of the wide cell pitch CSTBT, which is limited to approximately five times the nominal device rating or about one third that of a conventional narrow cell pitch trench gate IGBT. The low short-circuit saturation current provides a short-circuit withstanding capability of about 20µs, eliminating the need for additional limiting circuits. Also, using the CSTBT structure increases the conductivity in the drift region to produce a low on-state voltage as shown by curve 5d in Fig. 7.

By selecting the optimal cell pitch, you can tailor the device for the most desirable tradeoff between short-circuit saturation current and V_CE(SAT). For applications that do not require as much short-circuit withstanding capability, you can use a narrow cell pitch to give a lower V_CE(SAT). A wider cell pitch can be useful for maintaining short-circuit ruggedness in higher voltage devices. To provide process flexibility with a minimum number of mask changes, a novel structure called Plugged Cell Merged (PCM) CSTBT was developed (Fig. 8). With this structure the cell pitch is adjusted by “plugging” some portion of the cells in a conventional high cell density device. This process allows the cell density to be optimized by changing only two masks.

The polysilicon in the “plugged” cell connects to the emitter electrode. This connection provides additional drain-to-source capacitance that helps to stabilize the drain potential under short-circuit conditions. The result is stable oscillation free short-circuit operation even under high speed switching conditions. The waveform in Fig. 9 compares the short-circuit behavior of CSTBT chips with and without “plugged cells.”

1200V CSTBT Characteristic

Fig. 7 compares the measured on-state voltage of the four chip structures shown in Fig. 5. The narrow cell pitch devices in Figs. 5a and 5b have lower on-state voltage compared to the wide cell pitch devices. These lower on-state voltages are the result of the reduced resistance in the MOS channel. The on-state voltages of the CSTBT devices in Figs. 5b and 5d are lower than non-CSTBT (IGBT) devices. This is the result of the CSTBT's stored carrier effect and its dramatic reduction of the diode's resistance compared to a conventional IGBT. The on-state voltage of the wide cell pitch CSTBT shown in curve 5d of Fig. 7 is lower than that of the narrow cell pitch trench gate IGBT, demonstrating that the effect of the CSTBT structure overcomes the increase of the MOS channel resistance. An advantage of the wide cell pitch CSTBT is its positive coefficient of saturation voltage. Fig. 10 shows that the VCE(SAT) will increase with increasing temperature at most normal operating currents. This characteristic allows parallel operation without matching.

Wide cell pitch devices have a small saturation current proportional to the reduced channel width (Fig. 6). Reduction of the saturation current in the MOS region due to the decreased channel width gives the rugged short-circuit capability desired for industrial applications. A short-circuit test waveform is shown in Fig. 11. This waveform shows a 15µs low impedance short-circuit with an applied collector to emitter voltage 800V. An added advantage of the wide cell pitch CSTBT is a large reduction in gate Miller capacitance.

References

Takahashi, H., et al. “Carrier Stored Trench-Gate BipolarTransistor (CSTBT) — A Novel Power Device for High Voltage Application” The 8^th International Symposium on Power Semiconductor Devices and ICs 1996.
Motto, E., et al. “Characteristics of a 1200V PT IGBT With Trench Gate and Local Life Time Control,” IEEE Industrial Applications Society 1998.
Iwamoto, H., et al. “New 1700V IGBT Modules with Non-Epitaxial PT chips,” PCIM conference 2000.
Nakamura, H., et al. “Wide cell pitch 1200V NPT CSTBTs With Short Circuit Ruggedness,” International Symposium on Power Semiconductor Devices and ICs 2001.