Microstepping Motor Driver IC Cuts System Design Time

Oct. 1, 2002
When dealing with problems associated with cutting design time, Allegro MicroSystems' A3967 EasyStepper translator could be the solution. This complete

When dealing with problems associated with cutting design time, Allegro MicroSystems' A3967 EasyStepper translator could be the solution. This complete microstepping motor driver has a built-in translator that simplifies system design and minimizes control lines (figure). Its output drive capability is 30V at ±750mA for bipolar stepper motors in full-, half-, quarter-, and eighth-step modes. The device includes a fixed off-time current regulator that operates in slow, fast, or mixed current-decay modes. This current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout (UVLO) and crossover-current protection.

The A3967SLB's translator includes step, direction, MS1 and MS2 inputs. By inputting one pulse to the STEP input, the motor takes one step (full, half, quarter, or eighth, depending on two logic inputs). Inputs MS1 and MS2 establish the microstep resolution. There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program.

A fixed off time PWM control circuit regulates current in each of its two output H-bridges, which limits the load current to a desired value. An external current sense resistor (RS), reference voltage (VREF), and a DAC's output voltage control the translator's output and set the H-bridge current at each step.

At power up or reset, the translator sets the DACs and phase current polarity to their initial home state, and sets the current regulator for both phases to the mixed-decay mode. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level. If the new DAC output level is lower than the previous level, the PFD input sets the H-bridge decay mode (fast, slow or mixed decay). If the new DAC level is higher or equal to the previous level, then the H-bridge operates in the slow-decay mode. This automatic current-decay selection improves microstepping performance by reducing the distortion of the current waveform due to the motor BEMF.

Initially, the A3697SLB enables a diagonal pair of source and sink outputs, and current flows through the motor winding and RS. When the voltage across the current-sense resistor equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the source driver (slow-decay mode) or the sink and source drivers (fast- or mixed-decay modes). RS and the voltage at the VREF input set the maximum value of current limiting.

The associated p. c. board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. Decouple the load supply terminal, VBB, with an electrolytic capacitor (>47 mF is recommended) placed as close to the device as possible. To avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. To increase noise immunity, always drive the logic inputs with a low source impedance.

To minimize inaccuracies caused by ground-trace IR drops in sensing the output current level, RS should have an independent ground return to the star ground of the device. This path should be as short as possible. For low-value sense resistors, the IR drops in the printed wiring board sense resistor's traces can be significant, so take them into account. Use of sockets should be avoided because their contact resistance can introduce a variation in RS.

The A3967SLB is supplied in a 24-lead SOIC with copper batwing tabs. The tabs are at ground potential and need no insulation.

Allegro Microsystems Inc., Worcester, Mass. CIRCLE 349 on Reader Service Card

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