New Control Method Boosts Multiphase Bandwidth

Multiphase buck topology is preferred for processors that are drawing increasing amounts of current at lower voltage. Common design practices limit the open-loop bandwidth of the control system to 10% to 20% of the fundamental per-phase switching frequency. However, with proper current sensing, modulation, and control schemes, multiphase dc-dc converters can achieve a much higher open-loop bandwidth.

As the number of phases increases, the control system theoretically should be able to take advantage of the higher sampling rate created by the multiphase timing. For a system with N phases, Fig. 1 shows the error voltage sampled by each phase as the comparator trips. Because the phases are shifted in time, the error signal is sampled N times faster. Due to this increased sampling, the Nyquist limit for a multiphase system should be between the fundamental or per-phase switching frequency and the equivalent multiphase frequency:

N × f_s

Where:

N = Number of phases

f_s = Per-phase switching frequency

Multiphase Model

Contrary to common belief, it isn't necessary to increase the current in all phases at the same time to facilitate the increased control loop bandwidth effect to achieve better transient response. Consider the transformation from the multiphase circuit shown in Fig. 2 to the single-phase equivalent circuit shown in Fig. 3. The voltage applied to the simplified output filter inductor is the average of the voltages applied to the individual phases. If the error amplifier commands more volts × seconds be applied to the output filter, this can be accomplished by simply turning on another phase sooner or turning off a phase later. You can accomplish this with the proper design of the PWM modulator, to be explained here.

The control system only cares that the appropriate total volts × seconds is applied to the output filter to obtain the total output current. As you increase the number of phases, the average volts × seconds approaches the ideal linear case. Fig. 4 shows the modulation behavior of an 8-phase system with double-edge modulation during a step load increase. The ramp in this example system has been set up with a 1-to-1 error voltage to duty cycle ratio. In this case, the average duty cycle is the sum of the states of the individual phases divided by the number of phases. If all eight phases were on simultaneously, the average duty cycle would be equal to 1. So here we are comparing the error voltage to the modulated average duty created in the equivalent circuit. Notice that the average duty cycle has both a DAC-like behavior and a PWM behavior. An important result is that as the number of phases is increased, the duty cycle applied to the output filter approaches the ideal value — as commanded by the error voltage when using double-edge modulation.

With this new understanding of the multiphase system, it's apparent that certain improvements must be made to the PWM control system to take advantage of increased sample rate. These improvements include continuous, minimum delay current sensing and double-edge modulation for the PWM. We'll illustrate these concepts and compare their benefits over conventional low side R_DS(on) current sensing and leading, trailing-edge modulation.

Control Loops

Modern controllers have multiple control loops. There's a loop for each phase to share or balance current, a loop for automatic voltage positioning (AVP), and a voltage loop. The current sharing loop should be slow with respect to the other loops in the system. Almost any method of current sensing is fast enough for current sharing. The AVP loop must be equally as fast as the voltage loop to create a resistive output and keep the system stable. This rules out any output current sense method that uses a sample-and-hold method, such as low-side MOSFET R_DS(on) current sensing. The sample and hold in the current loop creates large delays in the feedback circuit, which show up as added phase delay and result in a diminished transient performance. Other system requirements, such as tight regulation and AVP accuracy and component tolerance, also rule out MOSFET R_DS(on) current sensing. The fastest current sense method available that consumes the least amount of power is inductor current sensing.

Inductor current sensing takes advantage of the inductance and the parasitic resistance of the output filter inductor to measure the current flowing through the output filter. This is done by creating a matching R_sense-C_sense filter time constant for the L_out/DCR time constant. The R_sense-C_sense filter integrates the voltage across the output filter inductor and provides a differential signal that represents the inductor output current (Fig. 5) ^[1].

The next problem that must be addressed is the modulation method itself. In currently available multiphase modulators, there's a set-reset flip-flop and a clock to maintain modulation timing. This set-reset creates fundamental large signal delays that have a negative impact on the control system performance and stability. Figs. 6 and 7 show, graphically, the clocked duty limiting effect of the set-reset. The set-reset prevents an increase in duty cycle in a clocked manner. Trailing-edge modulation takes a relatively long time to increase duty cycle, and leading-edge modulation takes time to reduce duty cycle. Another proven modulation method in addition to leading-edge or trailing-edge modulation that's the obvious choice for a high bandwidth multiphase system is double-edge modulation.

Double-Edge Modulation

Double-edge modulation removes the set-reset from the pulse-width modulator and allows the comparator to directly control the pulse width applied to the output filter. It accomplishes this by comparing the error signal directly to a triangle waveform of fixed frequency and amplitude. When the error voltage (V_ea) is less than the ramp voltage, the input voltage is applied to the output filter. When the error voltage is greater than the ramp voltage, the voltage applied to the output filter is switched to ground (Fig. 8, on page 41). The double sampling provides reduced phase delay in the control loop over single-edge modulation and solves the large signal issues related to the set-reset. The added benefit of double-edge modulation is that it doubles the sampling rate of the error signal. Fig. 9, on page 41, shows that double-edge modulation samples the error voltage 2 × N faster than the single-phase switching frequency.

The combination of inductor current sensing and double-edge modulation minimizes the control loop delays. Fig. 10 shows the improved multiphase control system.

To demonstrate the issues with the traditional modulation methods and show the advantage of double-edge modulation, several 8-phase models based on the circuit of Fig. 10 were created. In these models, the loop bandwidth was pushed up to the per-phase switching frequency of 1 MHz to compare the effects of leading-edge, trailing-edge, and double-edge modulation schemes on dynamic response. These models were identical except for the modulator itself. The models were ideal and contained essentially no delay. The set-reset and the comparator and phase node drive were ideal. Both leading- and trailing-edge modulation used a set-reset.

Fig. 11 shows the gain-phase plots from the state average model. The system loop gain is the sum of the current and voltage loop gains in this type of control system. The system loop bandwidth is nearly 1.5 MHz and has an ideal phase margin in excess of 50 deg. Fig. 12 shows the low bandwidth current share loop.

Fig. 13 compares the transient response of the system with double-edge modulation vs. the same system with leading-edge modulation. Notice the dramatic overshoot of leading-edge modulation when a step increase in load is applied to the system. This is caused by the set-reset in the leading-edge system holding the phases on until the clock commands the cycle over. Also, the leading-edge system shows additional overshoot when the load is released. All processor regulators operate at a low duty cycle. This results in duty-cycle saturation issues when the load is released. Overshoot is one of the biggest issues with processor dynamic regulation. System designers often add more capacitance to lessen the impact of the overshoot caused by the leading-edge modulation and add cost to their regulator design.

Fig. 14 compares the transient response of the system with double-edge modulation vs. the same system with trailing-edge modulation. Notice the set-reset creates a fundamental delay that prevents the controller from turning on the phases as soon as the error voltage indicates they are needed to address a step load increase condition. This causes a large undershoot when a load step is applied, as compared to the state averaged model. In addition, an oscillation of some type has begun to show up in the trailing-edge regulation.

Fig. 15 shows the error voltage comparison during this event. The error voltage with double-edge modulation recovers 250 ns faster than the trailing-edge modulated system and does not saturate. Fig. 16 compares the ideal state average system with no delays to the double-edge modulated system. It shows the state averaged model and the switching model agree, and that bandwidths of 1.5 MHz were achieved. They are nearly identical except for the switching ripple.

To further illustrate the potential advantage of double-edge modulation, the loop bandwidth was further increased in the system to more than 3 MHz, as shown in Fig 17, on page 44.

Fig. 18 compares the ideal state average model with zero delay to double-edge modulation. The two cases are still nearly identical, and the system is still stable. In a real-world application, there are concerns with noise, driver delays, error amplifier gain bandwidth limitations, and comparator delays. These issues will ultimately limit the ability of the system to achieve higher bandwidths.

Based on these simulations, double-edge modulation, combined with a fast current measurement method — such as inductor current sensing — is superior to other forms of modulation for the multiphase processor regulation system. This methodology could provide a path to higher performance regulation without further increasing the multi-phase switching frequency beyond 1 MHz.

References

Xunwie Zhou, Xu Peng, Fred C. Lee, “A High Power Density, High Efficiency, and Fast Transient Voltage Regulator Module with a Novel Current Sensing and Current Sharing Technique.” IEEE APEC 1999.

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