Tackling Complex Testing of New DC-DC Converters
In recent years, the development of new board-mount dc-dc converters has been incremental, focusing primarily on increases in power and reductions in real estate. For the most part, product advancements could be characterized as cramming more Watts (or amps) into a square inch of application real estate. Package sizes were decreasing and power-per-package increasing to the point of predictability. This resulted in the standard dc-dc test suite that most customers have come to require and expect. While dc-dc manufacturers' production testers continue to provide measurement of voltage accuracy, efficiency, line/load regulation, and transient response among other performance criteria, new applications and products are increasing the testing challenges.
Application complexity pushes the developers in the dc-dc market to offer new products at an amazing rate. On par with the competitive IC market with new product announcements, modern converters target specific applications and are tailored to meet the technology needs of sophisticated products. In particular, double-data-rate (DDR) memory applications, the proliferation of complex ICs (DSPs in particular) whose supply currents are load dependent, and the need for integration of product features for a “smarter” dc-dc pose some interesting test challenges.
DDR memory applications require the termination device to provide both current sink and source capabilities. Additionally, the output voltage for the termination of DDR memory is proportional to its applied (VDD) voltage. The proliferation of data transfer rates and compute device capabilities has resulted in the need for incredibly fast transient response or current slew rates from the converter. System control devices and the effort to create high reliability systems expand the digital interface or communication protocols associated with control and monitoring of dc-dc converters.
The technology advances of today's dc-dc converters are no longer incremental changes of space and power. The functionality being created leads to landmark changes in tester design.
Double-Data-Rate Memory
The dc-dc converters designed for driving DDR memory and its terminations have two characteristics that distinguish their testing from traditional converters. The DDR power converters must have the ability to source current as well as sink current while regulating their output voltage. Test development to confirm accurate functionality of sink/source requires a power source at the output. The test configuration must also contain the ability to transition the load-side power source to the output of the unit under test. The ability of the unit under test to regulate output voltage through the zero current point from positive current flow to negative current flow is crucial.
Standard power supplies have been designed to ensure that reverse currents aren't allowed to flow into the dc-dc converter. For this reason, production test equipment has been limited to a loading device at the output. New test devices will need to be fitted with a source device and the associated logic to provide smooth transition from loading device to source device and vice versa.
Fig. 1 shows DDR memory architectures in a simplified manner. DDR termination voltages (VTT) must track the supply voltage (VDDQ). The termination voltage must be equal to VDDQ/2 and maintain an accuracy of ±3%. Additionally, the reference voltage (VREF) must maintain a 40mV tolerance to VTT. Fig. 2 demonstrates this spatial relationship. Output regulation for the termination voltage can no longer be measured in comparison with a static voltage reference.
Since the termination voltage must now contain a voltage-tracking feature, a static reference won't be sufficient. The tracking requirement will replace the standard voltage reference with an interface requiring tester control to vary and monitor the relationship between input reference and output voltage of the DDR memory termination voltage.
High di/dt
New converters with high output-current slew rates (frequently associated with DSP and network-processor loads) present multiple challenges to production testers. In today's switching dc-dc, high di/dt is most often achieved by increasing the switching frequency and/or decreasing the output inductance. Additional steps are then taken to counteract the performance losses associated with reducing the inductance.
The basic design approach highlights the need for test equipment to minimize the inductance at the converter interface. Low inductance paths are absolutely crucial. Traditional test equipment has minimized the effects of resistive loss, while high slew rate testers will need to address inductive properties as well. Any additional inductance between the slewing load device and the DUT will rapidly degrade the DUT's ability to react and respond to current transitions.
Many dc-dc converters with high di/dt are assembled in surface-mount packages to minimize the parasitic inductance associated with through-hole pins. Such devices can't be “pushed” or “pressed” into test sockets without risking lead coplanarity. Fig. 3 demonstrates how spring-loaded pins can be used to accomplish a low-impedance contact with an SMT device.
Most contemporary, off-the-shelf, electronic-load devices aren't capable of 100A/µs slew rates in no-load to full-load transitions. In contrast, a number of contemporary dc-dc converters produce 50A/µs to 100A/µs slew rates and will soon approach 500A/µs. Even if the loads were capable of such slew rates, the distribution associated with cables and the standard interface represents unacceptable inductive losses.
The slewing load device must be located close to the source. Custom load circuits must be developed and mounted right on the interface card for the DUT. The block diagram in Fig. 4 represents one approach to providing local switching devices capable of confirming 100A/µs slew rates.
The oscilloscope trace in Fig.5 shows the transient response of a unit under test on cursor No. 1, and the gate signals of the switching devices on cursors No. 2 and No. 3. This switching scheme enables unit measurement of high di/dt transitions from no load to 50% load, 50% load to full load, full load to 50% load, and 50% load to no load. Control of the associated timing circuit and selection of the load resistors can be modified to target various load levels.
A variable resistance device placed in series with the gate of the switching devices allows variable slew rates. The RC network that's developed with the varying device and gate capacitance present in common switching devices allows for testing at various slew rates. Tests performed as outlined by the block diagram circuit demonstrated slew rates from 1A/µs to 300A/µs.
Communication, Command and Control
While the two previous test advancements are associated with new application demands, communication, command and control (C3) advancements are byproducts of increasing system complexity and the need to communicate with and control future dc-dc products. In particular, the integration of microcontrollers is enabling dc-dc developers to add product features that simultaneously meet reliability goals, technology expectations, and cost pressures. Unsurprisingly, this poses yet another distinctly different challenge to test developers.
To cost effectively exploit microcontrollers, test units must be capable of programming the microcontrollers in circuit. The tester must then verify the proper program has been loaded or flashed to the microcontroller. Finally, the tester hardware and software must test all associated functions/features provided by the microcontroller.
These new product features include the ability to execute complex timing functions or to perform math functions such as multiples of voltage and current to account for power limiting. Furthermore, hierarchical schemes to provide priority to fault conditions are easily executed. Microcontroller usage opens long lists of possibilities for dc-dc converters and equally long lists of test challenges.
Interface protocols for programming, controlling, and polling microcontrollers such as I2C represent the likely future of converter interface for the user. Digital comm ports on the converters allow for margining functions, voltage set points, status polling, and even flashing of new application software code to the converter. Numerous queries and commands will all be communicated to the converter from the system host with the use of minimal product pin count.
As these features emerge, the tester will need to create various situations to verify the accuracy of polling features, exercise control features, and verify the ability of the units to receive new source code. With products already in development with features demonstrated in Fig. 6, the test challenges are immediate.
Daunting Challenges Ahead
The dc-dc converter market is highly competitive with many competent participants making sizable investments in new product development. Experienced users expect a steady flow of higher-performing, increasingly complex products — and testing those products is adding many product-specific tests to the traditional dc-dc test suite. At the same time, manufacturers seeking to produce high quality, reliable products are hamstrung by the price competition and low margins of the maturing market. It all presents a daunting challenge to production test equipment and the engineers who develop that equipment.
Application-specific performance characteristics and features, such as nonstandard termination voltages, outputs that both source and sink current, and communication protocols, are dictating tester overhauls and new ways of developing products through production. More than ever, test requirements must be thoroughly understood and test approaches thoughtfully planned to yield quality, high-performing products for the end customer.
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