Integrated Building Block for Dual-Output Buck Converter

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Designing power solutions for today's information technology boards that handle multiple tasks at much faster rates is complex. As these boards must process more and more data, they incorporate multi-GHz microprocessors, dual-logic ASICs and other high-performance devices like FPGAs on a single card. These new-generation devices can require two operating voltages per chip: one for the core, which is around 2.5V or 1.8V and rapidly moving downward, and the other for the I/Os, which is higher and around 2.5V or 3.3V.

It is not surprising to see the need for multiple operating voltages on new-generation NPU, ASICs, FPGAs or any other high-end application board. Until now, such requirements were addressed using multiple single-output isolated dc-dc converters. However, with rising current requirements and declining voltages, along with stricter regulation tolerances and faster slew rates, multiple isolated power converter solutions are not as effective in such applications.

These isolated converters are not space efficient and can cause significant losses because of the resistance of the long interconnect lines. Under such conditions, maintaining high overall efficiency and tight point-of-load (POL) regulation becomes challenging.

To alleviate these power problems and to make the designer's job simpler, International Rectifier has developed a power management solution for POL applications. It uses a unique device as a power stage building block in a two-stage distributed power architecture (DPA). By using a handful of external passives around this block, a designer can build a high-performance 2-phase, dual-output synchronous buck converter for several of the load-voltage requirements.

Distributed Power Architecture

For many reasons, including high efficiency and tight regulation at low voltages, DPA has become an attractive architecture for multiload or multivoltage applications. Aside from bringing dc-dc converters closer to the POL, DPA allows flexible POL converters to be used and optimized specifically for the intended application. POL delivers adjustable output voltages that can be trimmed at the load if necessary. It also features control complex sequencing and a tracking function specific to the type of processor used. Furthermore, to ensure proper operation of the system, the multiple operating voltages on a system card must be initiated in a proper sequence per the processor manufacturer's specification.

Within a communications system, there are multiple DPA architectures. The most common way is to distribute a 48V bus across a backplane. Several choices exist for selecting the intermediate bus voltage from the output of the 48V isolated converter, depending on power level and quantity of rails. The most common on-board distribution schemes today are 3.3V and 12V. As a general rule, the 3.3V rail is typically chosen if the power levels required on the system card are <60W and 12V is generally used for levels >60W. A new intermediate bus voltage architecture is gaining popularity and this is nominally set around 8V, which is generally good for 60W to 150W cards. One example of how to implement this rail is the recently introduced dc bus converter chipset, using International Rectifier's IR2085S. This uses a dc bus converter with no output voltage regulation, which reduces the cost and complexity of the isolated portion of the converter by as much as 50%.

An unregulated intermediate bus can be used as input to the POL converter. Because the POL takes care of all regulation, unnecessary double regulation can be eliminated, reducing component count and complexity of the system's isolated portion while improving electrical performance.

As an example, an 8V intermediate bus architecture can be considered (Fig. 1) and all other voltages must be derived from this 8V bus. To minimize compound efficiency loss, which can be significant at times, the POL converters should offer efficiency close to or above 90%. For instance, if two 90% efficient converters are used in series, the overall result can be as low as 81%. Therefore, the POL converters deployed in this scheme must achieve high efficiency to minimize the throughput efficiency loss. In this particular example, the bus voltage of 8V was produced at 96% efficiency, and the iP1202 produced an efficiency of 92% with a load current of 8A. This provides a respectable overall efficiency of ˜88%, with a lower-cost architecture.

System designers must consider many other factors. For instance, there are several ways in which start-up can be programmed to properly track multiple voltages on a given board. And the load specification dictates the method most suited for the end application. In short, three such methods can be implemented to control the power-up sequence. Sequential power-up first turns on the core voltage. When it reaches regulation at the desired voltage set-point, it turns on the second I/O rail. In effect, this technique can be used to delay the start-up of the second rail at some predetermined time after the first rail is turned on. The second type of start-up is the ratiometric method: The two supplies are turned on simultaneously, reaching regulation at their respective setpoints at the same time. In this method, the two rails are controlled with different slew rates, so that the two different voltages are realized at the same time.

The simultaneous power-up sequence (also known as output tracking) is the third approach to power sequencing. Both the rails start up simultaneously and rise at the same slew rate. As a result, the lower voltage rail reaches regulation first, and the higher rail reaches regulation later (Fig. 2).

In solutions where such control techniques are not deployed, diodes are connected between the core and I/O rails to ensure that the supply voltage start-up sequencing is maintained within the tolerance specifications. However, such circuit technique is appropriate for voltages that are close, like 3.3V and 2.5V. With reducing core voltages and high I/O voltage, the differential is becoming much greater, warranting the use of techniques described above. In designs where exact rise times and/or sequencing of POL converters are not available, MOSFETs can be used at the output of each rail. In this case, each supply is permitted to rise to its specific output voltage setpoint, and then the MOSFETs are used to control the sequence in which each output is delivered to each of the loads. As MOSFETs have a specified on-resistance and operate as 100% duty-cycle switches in this application, they further add to the power loss of the circuit, causing a significant cut in overall converter efficiency. Although this loss can be slashed by paralleling MOSFETs, it adds to the cost, board space and complexity of the solution.

Simple Solution

To offer a solution that addresses the above issues and delivers the desired features, IR has applied its iPOWIR packaging technology to create an integrated building block.

Applying expertise in power system design and the chipset interaction, it has integrated PWM controller and driver functions with associated control and synchronous MOSFET switches, Schottky diodes and input bypass capacitors in a single package. For maximum performance, the power components used in this single package have been closely matched, with optimized internal layout. The result is a single device that can now be treated as a building block toward the design of a high-performance 2-channel synchronous buck converter.

As depicted in Fig. 3a, the only components needed to complete this dual-output power supply are the output inductors, output capacitors and input capacitors, in addition to a few other passives. Both the channels of the power supply operate from a common input. Because the internal topology is synchronous with fixed-frequency voltage-mode control, the two outputs can easily be paralleled to achieve a single output voltage with twice the current handling ability shown in Fig. 3b. A 180-degree out-of-phase operation is used for single or parallel output, and the benefits from increased ripple frequency can be seen with external component count and size reduction. Plus, iP1201 and iP1202 can be powered directly from the bus voltage, eliminating the need for external bias circuits, and reducing additional external components and design complexity. This new building block measures 9.25mm × 15.5mm × 2.6mm, saving the designer precious board space and making valuable contributions to the desired power density.

By using a simple resistive voltage divider for each channel, the output voltages are independently adjustable for the iP1201 and iP1202, allowing all the common input and output rails in the computing and communications system to be addressed with just two devices. In fact, these devices are rated to handle up to 15A up to an elevated board temperature of 90°C if the case is controlled to 90°C. Without regulation of the case temperature and with no top-sided heat sink or airflow, the products still delivers currents in the 11A region. By comparison, alternate solutions undergo significant derating at elevated temperatures by as much as 50%.

With the addition of a capacitor to each of the independent soft-start pins, this solution offers power-sequencing control to each of the outputs. To limit the inrush current during start-up, the soft-start function provides a controlled rise of the output voltage. Consequently, by combining the two soft-start pins appropriately, the user can select the most pertinent output load sequencing method as outlined above.

A hiccup pin is available to set overcurrent protection protocols and can be configured to either latch or hiccup (auto-restart) when a short circuit is detected. Hiccup is key in today's end telecom or networking systems, many of which are in remote locations, so increased up-time and auto-restart capabilities reduce maintenance costs and inconvenience that can effect QoS. In addition, the iP1201 and iP1202 can be externally synchronized with other POLs, such that input EMI filtering can be simplified.

A complete schematic for a dual-output synchronous buck converter using iP1202 is shown in Fig. 4. In this design, the voltage at V_OUT1 is 1.5V, while on the V_OUT2 channel is 2.5 V. Measurements indicate that it obtains an efficiency of 92% at 8A load for 8V_IN and 1.5V_OUT and 2.5V_OUT. The operating switching frequency range for the unit is 200kHz to 400kHz and offers features such as overcurrent and overvoltage protection, hiccup, power good signal and thermal shutdown. To address a wide range of system requirements, the iP1201 and iP1202 are designed to operate between -40°C and 125°C.

To obtain up to 30A current from a single output, the two outputs can be paralleled to form a single output. In this mode, one error amplifier controls the output voltage, while the other amplifier monitors the inductor current information for current sharing. Because two 180 degrees out-of-phase outputs are combined into one, the two inductor current ripple currents cancel each other to result in a substantial reduction of output ripple current — thus, permitting smaller output capacitors.

To enable accurate thermal design of the pc-board, this building block is also constructed to guarantee a power loss limit and safe operating area. Such calculations are complex and time consuming in traditional discrete-based power circuits, wherein many first-order, power-loss-dependent variables from the power semiconductors must be taken into account. Add to this the virtual elimination of second-order layout and stray parasitic loss effects that are more difficult to account for accurately in the initial design phase.

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