Powerelectronics 1461 S 2
Powerelectronics 1461 S 2
Powerelectronics 1461 S 2
Powerelectronics 1461 S 2
Powerelectronics 1461 S 2

Bi-Phase PWM Controller Sets New Standards

Oct. 1, 2003
Many design teams are focused on increasing the switching frequency of their buck converters to improve ripple characteristics and performance

[For a copy of this article in PDF format, which displays figures and equations,

click here.

Requires Adobe Acrobat Reader,

free download


The challenges facing designers of PWM controllers go far beyond just rapidly increasing power. Many design teams are focused on increasing the switching frequency of their buck converters to improve ripple characteristics and performance. Others have recognized that requirements for the rate of change of current in advanced processors are going up continually, while the regulation tolerance continues to get tighter. To make matters worse, equivalent series resistance (ESR) and equivalent series inductance (ESI), caused by poor converter layout practices, can greatly compromise the regulator performance by introducing voltage glitches that are difficult to compensate for. In such an environment, step responses to changes in current levels become critical, both for overall reliable operation and transient response. This is particularly true in the case of negative-going transients that are destructive to today's advanced processors, but are often not compensated for.

While some suppliers focus on adding many more phases to their PWM controllers, others work to develop dual or bi-phase devices that can handle the output current requirements of today's most advanced processors and are implemented with architectures that can be efficiently cascaded to meet future device requirements. Microsemi has developed a superior version of the latter type of devices, the LX1677. This IC, shown in Fig. 1, features bi-phase PWM switching regulator stages for use over a frequency range of 150kHz to 1MHz with integral MOSFET drivers capable of controlling a core supply that delivers up to 70A. Designed for use with AMD Athlon 64 and AMD Opteron processors, this device embodies advances in load sharing and transient response required by advanced processors while holding the line on cost and complexity of implementation.

New Load-Sharing Technique

Most load-sharing techniques on the market are centered on sensing the voltage drop across a known resistance to determine output current provided by each phase of a multistage converter. These values can then be compared and fed back to force the output of one or more stages to increase or decrease to a desired level. A common practice is to add a series current sense resistor to the output path. However, this adds additional components and significant cost to the target converter design. Several suppliers have developed innovative techniques that use the RDS(ON) of the primary MOSFETs within the converter as the sensing element. But many of these implementations suffer from severe signal-to-noise degradation due to MOSFET switching characteristics and RDS(ON) variation.

Microsemi has developed the LoadSHARE technique that depends on forcing equal voltages across each inductor in the output of a multiphase buck converter topology. This sensing technique doesn't require sensing elements to be in the high current path, resulting in the use of common, inexpensive components. One end of the inductance from each phase is tied to the output capacitance, so all inductors have identical voltages at the converter output. The other end of each inductor is tied directly to the MOSFET output (phase node) of each phase; voltage here at the input side of the inductor will vary directly with the current output from each phase. The idea is to use voltage differences at the inductor's input end to force the potential across the inductor of any phase to equal that of another.

This can be done using two simple feedback loops in parallel, as shown in Fig. 2. The primary loop would provide normal voltage feedback directly from the output of the converter to set the output voltage of the combined phases. The secondary feedback loop would sense the phase node of each switching phase via a low-pass filtering, then amplify and integrate the voltage difference. This resultant error signal can then be used to force an opposing increase or decrease in duty cycle of each switching output — thus, the currents flowing through the inductors are equal.

This technique by itself provides for current matching to be better than 5% tolerance without optimizing components. Further matching is possible with the use of an inexpensive thermistor sensing the MOSFET temperature of each phase. The resultant thermal balance has been shown to keep power components within 5°C of each other, even with mismatched impedance paths, resulting in higher reliability operation.

With the LoadSHARE topology, it's also possible to unbalance the output of the two phases of the buck converter so that one will supply more of the current than the other. This is accomplished for special purposes by feeding a dc bias into the differential amplifier of the current feedback loop controlling each of the phases. The current output of the second stage will then be forced to offset from that of the first by a fixed amount. This imbalance can even be imposed when converting from different voltage sources.

Response and Correction

Extreme step changes in current output are common in advanced processor systems as the device powers sections up or down to handle changes in computing load and to institute sleep-mode power management strategies. Transients also are common, which can result from supply voltage changes or other external factors. Both must be compensated for to protect the processor circuitry from destruction. When using a conventional buck converter topology, rapid decreases in current are virtually impossible to correct because the low voltage available for feedback isn't enough to generate a forcing response.

The LX1677 PWM controller uses a unique strategy to accommodate and compensate for all these potential changes in current output (Fig. 3). First, on sensing the current step, it brings both phase outputs into phase and operating at 100% duty cycle. It then turns on an on-chip switching Hysteretic regulator capable of switching at frequencies as high as 10MHz to source or sink additional current at the output. This third regulator is only active for brief times when high di/dt loads affect the output of the converter.

This transient correction loop (TCL) converter sources current through a significantly smaller inductance than the primary phases, allowing for a large amount of current at high slew-rates to be summed into the output node when required by an out-of-range condition. Within the loop, a fast differential-feedback summing amplifier is employed to track changes in output voltage at the microprocessor socket. This amplifier output is compared to the reference command voltage in two separate comparators, and the resultant offset or error signal from either comparator determines corrective action, turning on a connected MOSFET to force current into or out of the output node to correct the voltage error. The low value inductor between the MOSFETs and the output node allows large amounts of current to be sourced or sinked quickly with excellent response characteristics (Fig. 4). This dual mode of operation provides the first built-in capability to respond to negative-going steps or transients, and facilitates pulling an overshoot in load current down to target levels to promote fast settling at the new current set point. The two outputs controlling the TCL MOSFETs are completely independent and can be used to control voltage droop only or voltage overshoot, only providing an extra degree of response control as desired. Using TCL in addition to commonly used droop compensation techniques greatly improves the performance of PWM regulator designs.

Cost of this implementation is insignificant when compared to the savings in output capacitance. In fact, use of this transient correction strategy reduces the need for output capacitance to high-speed decoupling under the processor socket, while eliminating all requirements for bulk capacitance at the converter output. Because they are on for short periods of time, each TCL MOSFET can be sized according to its peak pulse current response, again allowing use of lower-cost components. In addition, the inductance used for this loop is inexpensive — on the order of 70nH, which is equivalent to a PCB trace or an air core inductor of a few turns.

The resultant performance benefit to offloading transient surges to the TCL is higher efficiency. Because the bandwidth requirement of the main phases is effectively decreased, the switching frequency can be lowered to minimize the peak inductor ripple current. Typical improvements are on the order of 20% for a load current around 4A when compared to competitive solutions. Lowered ripple voltage is also an ensuing benefit.

This much is clear: As current demands continue to climb with tighter regulation requirements, architectures like LoadSHARE and transient correction are required to meet the upcoming power demands of tomorrow's microprocessors to improve performance and lower system costs.

For more information on this article, CIRCLE 334 on Reader Service Card

More on Buck Converters

Buck-Converter Design Demystified Optimizing Voltage Selection in Buck Converters Power Conversion Synthesis Part 1: Buck Converter Design Improving Efficiency in Synchronous Buck Converters


To join the conversation, and become an exclusive member of Electronic Design, create an account today!