A One-Chip Solution for Electronic Ballasts in fluorescent lamps

An electronic ballast, in simplistic terms, takes a mains supply and transforms the energy to a storage capacitor, which in turn powers a half bridge to provide frequency-controlled power for a fluorescent lamp. Typically, the electronics for this solution are implemented in three different integrated circuits (ICs), which require fabrication in both high-voltage and low-voltage process technologies. A high-voltage (400-V compatible) process is used for the input section, and a low-voltage process is used for the digital control IC. Efficiencies in manufacturing could be made if all three functions — the input section, the control IC and the lamp power control IC — could be integrated on a single chip. However, doing so presents technical challenges, particularly in combining 12-V FET drivers and low-voltage circuits on the same chip in a standard CMOS process technology.

Electronic Ballast Circuit Background

Fig. 1 shows a typical electronic ballast. The entire system can effectively be split into three different functional blocks or sections. The input section comprises a mains supply, boost converter and energy-storage voltage regulation. A second section consists of the half bridge, the load and the lamp power control (not shown), while the third section contains a digital control chip or ASIC (not shown). Dividing the path from the mains supply to the load into two nearly independent sections makes system dimensioning flexible and allows the regulation loops to be individually optimized.

The mains supply that enters the first IC is rectified and fed to a boost converter (power factor corrector or PFC). A typical storage-capacitor voltage (V_bus) is 400 V, which is above the maximum rectified ac mains supply; hence, the PFC is working as a boost converter. The stored energy supplies the half bridge, comprising two external NMOS power FETs in push-pull configuration. The storage capacitor also provides power to an auxiliary circuit with a small transformer to drive the half bridge's high-side gate. The lamp power is frequency controlled. Therefore, an inductive impedance with a dc decoupling capacitor is in series with the fluorescent lamp. Typical frequencies of operation are above 40 kHz.

Of the three functions, the PFC standard IC is usually fabricated in a 400-V compatible Bipolar-CMOS-DMOS (BCD) technology with analog regulation of the PFC. A full-custom ASIC in a 0.7-µm CMOS process^[1] with analog regulation of the lamp power provides the digital lamp management. The half-bridge driver is a standard IC that establishes the high-side and low-side driver for the output.

Integration of these functions raises the issue of which technology should be used. The most popular approach is to select a high-voltage compatible BCD technology that makes it easy to design interfaces to the power electronics environment. A disadvantage is the low digital-integration capability of these processes that make highly integrated systems on a chip (SoC) not cost effective from a commercial point of view. If, however, an SoC solution in a standard 0.35-µm CMOS manufacturing process is used, all inputs to the SoC ASIC are voltage limited, and the outputs are compatible with the gate-driving voltage of external power FETs. Although this approach may require additional discrete components, it opens the opportunity for a highly integrated SoC in a power electronics environment.

Input and Output Sections

One section within an SoC ASIC is the boost converter control, as depicted in Fig. 2. Four input signals feed the control logic that switches the on-chip driver for the boost-converter transistor. The input signals to the SoC ASIC are voltages reduced by external resistive-voltage dividers. These signals are taken from the mains-rectifier output V_RM, the drain connection V_MP of the power transistor M_P of the boost converter, the shunt R_P and the voltage V_BUS across the energy-storage capacitor.

Lamp power control
The system-output section, including the interfaces to the lamp-power regulation circuit, is depicted in Fig. 3. The lamp voltage and the current through the low-side driver transistor are used as the input for the output load regulation circuit, to control the half-bridge drivers. As a result of the dc decoupling capacitor, the average current through the shunt represents the part of the lamp current that contributes to the real output power. Other techniques are possible for measuring the current through a shunt at the V_SS connection of the lamp^[1]. The low-side transistor, M_L, is driven directly by the SoC ASIC, whereas the high-side transistor, M_H, is driven by a small transformer performing the level shift from the half-bridge output node to ground V_SS. The transformer itself is driven by the common on-chip FET driver.

Blocks in a Single-Chip Ballast

The main blocks of a one-chip solution for the electronic ballast (Fig. 4) are the analog interfaces, the support modules and the output drivers. Later, we'll discuss the structure of the digital core section.

Support functions include on-chip voltage regulators, bandgap reference, voltage and current references, fuses, oscillator and test blocks. The fuses enable adjustment of voltages, currents and the 10-MHz oscillator, which has an overall accuracy of 3%, including initial accuracy and temperature.

The comparators and the time-multiplexed sigma-delta analog-to-digital converter (ADC) are the analog inputs. The ADC, together with the decimation filter, gives 12-bit resolution with a 3.3-V input range in 100 µs. The silicon area of the analog part is 0.25 mm² with a current consumption of 700 µA. The decimation filter has 5000 gates, including offset and gain calibration circuitry, running permanently in the background.

Fig. 5 shows the relationship between the analog and the digital clock. The comparators and the switched-capacitor (SC) integrators of the sigma-delta ADC are run with the undelayed oscillator clock, whereas the digital core works on a delayed clock from the sigma-delta ADC clock generator. This clocking scheme and the intelligent signal evaluation — which skips measurements while the fast drivers are switching — gives the system excellent noise characteristics.

Digital Core of the SoC ASIC

The digital part is split into three functional groups (Fig. 6). These include the service blocks to operate the chip, functional blocks to perform the chip's duties and the integration group, which connects the digital part to the analog surroundings.

The service modules, consisting of the five functions shown on the right-hand side of Fig. 6, ensure basic internal operations of the electronic ballast chip. CLK_GEN switches on/off the different clock trees, depending on the mode of operation. RES_GEN distributes the reset signal, while SCAN_CTRL provides all the block connections to the scan test inputs and outputs. It also sets special signals to do some switching in the digital blocks to increase the scan test coverage. The FUSE_CTRL block contains the fuse programming interface, which is also used on the ATE to select the test modes and analog blocks to be tested. It also reads out the fuse values during startup for reference value adjustments. STARTUP_CTRL is responsible for a proper startup of the digital system and switches the different modes of operation, such as test, scan, fuse and low power, depending on the requests given by the logic or the user interface.

The second group of functional blocks enable the system operation. This includes the ADC_CTRL block, which converts the sigma-delta bit streams into 12-bit values and sets up the signal-select input sequence for the analog multiplexer. The digital power factor corrector (DPFC) contains the proportional integration (PI) regulator and a distortion improvement block, as well as an output-signal controller that converts the calculated cycle times into on/off signals for the FET driver^[2]. The digital lamp-control circuit (DLCC) is responsible for calculation of the half-bridge output period time and control of the on/off switching of the corresponding FET drivers. Additional special functions implemented in this block include PWM operation for lamp ignition or immediate shutdown in failure conditions, such as overvoltage or lamp removal while the lamp is on.

A finite state machine (FSM) contains the control program for all the system's features (Fig. 7). It has a set of eight commands and resources such as adders, a time-out counter and an interrupt service block. The FSM is split into the control unit and its ROM part. Thus, the system designer can change the FSM program with minimal impact on the ASIC designer's work. The ROM table is generated automatically by the customer from one of the customer's flow charts, which are checked by system simulation tools, such as Simulink. The FSM consists of a 5-bit-wide address vector and a 64-bit-wide ROM vector.

The third group (see the Interface block in Fig. 6) contains only one block that controls the interfacing between the digital and analog part. It assures that kickback noise from the analog part can't influence digital inputs. It also ensures testability of the semiconductor device during production. All signals that cross the analog-to-digital boundary (and vice versa) are routed through this block, except the global clock and reset signal.

Fig. 8 shows the chip photograph of a production solution based on this integration approach. Manufactured by Dialog Semiconductor in a standard 0.35-µm CMOS process with triple metal, double-poly capacitors and high-resistive poly layer, it yields a total chip area of 4.4 mm². Note that it is produced in a standard high-volume process, ensuring manufacturability in any 0.35-µm technology. Measurement results for signals in the 3.3-V and 13-V domains are shown in Fig. 9.

Process Selection

When integrating electronic ballast functions in a standard manufacturing process technology, don't overlook the complexity of incorporating features such as several on-chip regulator loops. For example, any noise on the chip impacts the regulation loops, analog inputs of the ADC and on-chip references. Therefore, it's important to minimize the effect of this noise for optimum performance.

New packaging technologies allow easy partitioning of high- and low-voltage domains and functions using a low-voltage IC for SoC integration. In Dialog Semiconductor's experience, the selection of a low-voltage technology is a critical aspect of the path toward a highly integrated device. To illustrate this, ballast devices now demand much more intelligent or “smart” control, which requires integration of various digital functions like microcontroller, flash memory and bus systems.

References

S. Zudrell-Koch, “Mixed Signal ASIC for Closed Loop Fluorescent Lamp Management Using Novel Digital Frequency Control Strategies,” Industry Applications Conference 2000, Conference Record of the IEEE, Vol. 5, 2000, pp. 3434-3440.
G. Marent, “Novel Electronic Ballast with Integrated Digital Power Factor Controller,” Industry Applications Conference 2003.
Fred C. Lee et al, “Technology Trends Toward a System-in-a-Module in Power Electronics,” IEEE Circuits and Systems, Vol. 2, No. 4, 2002.

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