Getting the Most out of Power Factor Correction

March 1, 2004
The relevant standard most power-supply designers follow for power factor correction (PFC) is the European norm EN61000-3-2. This applies to most off-line

The relevant standard most power-supply designers follow for power factor correction (PFC) is the European norm EN61000-3-2. This applies to most off-line supplies with an input power of 75 W to 1000 W. With this added cost burden, we should be looking for ways that PFC can help us.

One of PFC's possible benefits is achieved by a design technique that has crept under the hood of many power supplies, particularly in Europe, but has gone largely unnoticed in the United States. Some power factor control ICs offer “synchronization capability,” but that phrase usually means the PFC is in-phase with the pulse width modulator (PWM). In general, this isn't conducive to lowering EMI. Thus, many engineers run the PFC and PWM independently (no synchronization), taking care to keep their respective switching frequencies spaced somewhat apart to avoid beat frequencies.

However, think of an alternative scheme: We know that the PWM draws current out from the bulk capacitor, whereas the PFC dumps current into it. What if we could make these opposing currents cancel? Maybe what we really want to do is turn on the PWM switch at the exact same moment as the PFC starts to turn off. This is an out-of-phase synchronization of sorts. Thus, we'd expect that the freewheeling current (coming out from the PFC diode) would head straight into the PWM stage (most of the time) without having to recycle through the bulk capacitor. Would this save on the capacitor rating? Indeed it would, and for a 400-V to 450-V capacitor, we're talking real money.

This synchronization scheme was introduced as an IC from Micro Linear (its power management group is now part of Fairchild) and was billed as the “industry's first leading-edge/trailing-edge modulation scheme” PFC/PWM combo IC. Though, if you think hard, you can do the same thing with a common PFC IC and a PWM IC. Simply command a clock reset of the PFC whenever the output of the PWM goes low.

In fact, mathematically, it can be shown that it doesn't matter whether we turn on the PFC when the PWM goes off, or turn on the PWM when the PFC goes off. Or, we can do it the elaborate way by trying to keep a constant clock frequency for both the PWM and PFC (sort of running their on-pulses back to back).

Because the PFC duty cycle varies from very low to very high values, and the PWM duty cycle is fixed, this “cancellation” works but by different amounts over the ac line cycle. Therefore, it's hard to provide any easy closed-form equation for calculating the net reduction in the RMS current. Unsurprisingly, no such detailed application information is provided even for the Micro Linear part. Perhaps this is why most engineers decide to stick to safer ground.

In Germany, this scheme was independently conceived and pioneered within Siemens AG by the author for a critical server power-supply project. Then, with the help of Dr. Karl Rinne, a complex Mathcad file was created to model this scheme.

Since then, much more modeling work has been done by the author. The results show that if we were picking a capacitor based on its ripple-current rating, then we would gain a significant reduction in its cost. The ripple current in the capacitor can be reduced, even compared to the case of a non-PFC front end. Finally, we find that PFC is working for us on a cost basis.

The reduction in the ripple current, as measured against a similar power supply with no synchronization, is a function of the duty cycle of the PWM stage. Over the input range of 90 Vac to 270 Vac, the reduction is a whopping 39.6% at PWM duty cycle of 0.33, just ideal for a forward converter PWM stage. It drops to 21.9% at a 0.5 duty cycle, making it plausible but not so tempting for a flyback.

In terms of capacitor heating, which depends on RMS squared, the savings are by no means mean. This idea was implemented successfully in Leipzig. It had a crowbar effect on the entire power-supply's configuration and cost, because so much more space became available that we could do it with only one single-sided power PCB, whereas our competitor had three such boards strung on the sides of the box, blocking the air flow as well.

Sanjaya Maniktala has more than 15 years experience with power supply and semiconductor companies, including Artesyn Technologies and Siemens AG. He holds masters' degrees in physics from the Indian Institute of Technology and Northwestern University, as well as several patents.

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