Tackling the Challenges of Power Dissipation

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Integrated circuit manufacturers are working furiously to reduce the package sizes of power devices for their customer base. This effort has been well received, particularly where portable applications are involved. Some of the newer packages in which these power devices are being housed include the 3 × 3 (mils) Dual-Flat-No-Lead (DFN) package (Fig. 1). This package's dimensions appear inadequate for ample power dissipation of power devices. However, a closer look shows the bottom of the device has a metal tab that can be used to dissipate power by soldering the package to the printed circuit board (PCB) metal.

Thermal resistance is one of the primary specifications that changes because of reduced package size. This change is done while power requirements are increasing. If a smaller outline device is required to deliver large currents and a reliable system is needed, thermal evaluations become an up-front design requirement. Using an easy thermal-evaluation technique, solid design guidelines are quickly produced for the PCB final product.

When looking at the thermal behavior of a circuit, the first pass can be done with some simple calculations. You might be tempted to use expensive thermal evaluation equipment to evaluate a working board, but the pencil calculation will provide ample information and save time.

From there, lab testing is in order. This testing will prove the calculated conclusions. Again, the testing doesn't require expensive equipment, it only requires a fabricated and assembled PCB with the devices installed. The PCB should be laid out with thermal dissipation techniques in mind. These techniques include the use of a solid-ground plane for a heat sink and the careful location of vias.

To illustrate the techniques used in a thermal evaluation, a low-dropout (LDO) regulator is chosen for this example. An LDO is used to convert a battery voltage to a lower regulated output voltage. Of all the power devices available for this function, the LDO provides the lowest noise conversion. An alternative device would be a switched-mode buck converter. Although this type of converter is typically more efficient than an LDO, it can generate switching noise on the power-supply bus.

The regulated output voltage of the LDO supplies power to the rest of the application circuit. However, a closer look at a battery-powered application family shows it isn't unusual to have more than one LDO in the circuit. For instance, the application circuit could have portions of the circuit that are powered by more than one voltage. An example of this would be where a higher voltage, such as 3.3 V, powers the analog portion of the circuit; the digital portion of the circuit is powered with a 1.8-V power-supply voltage. Another application type is where several portions of the circuit require some degree of isolation but also require the same voltage. In this type of system, some portions of the circuit can be turned off, while others are left on. In yet another application, power sequencing of various portions of the circuit is required.

These kinds of applications could prompt a designer to use a dual LDO instead of a single LDO. The dual LDO conserves board space and typically improves overall price. Both features are attractive, but the dual LDO dissipates the power of both LDOs in one package. The smaller package, whether it contains a dual or a single LDO, may have a higher thermal resistance.

To summarize, this dual LDO device dissipates more power (or heat) and is housed in a less-efficient thermal package. These conditions are aggressive, but the challenge of dissipating the heat can be worked out as follows.

An example of a dual LDO is the TC1301B from Microchip Technology Inc. One of the smaller geometry packages that house this dual LDO is the 3 × 3 (mil) DFN. Figs. 1 and 2 show a diagram of the DFN package.

This device combines two LDO regulators and a microcontroller RESET function into a single 8-pin, 3 × 3 mil DFN package. Regulator number one (LDO₁) inside this package has a dropout voltage of 104 mV at 300 mA output current (typical). Regulator number two (LDO₂) has a dropout voltage of 150 mV at 150 mA (typical). ^[1] The maximum allowable steady-state junction temperature of the TC1301B is 125°C. The TC1301B has a convenient thermal-shutdown feature that facilitates thermal evaluations. This device goes into a thermal shutdown mode at 150°C (typical).

The TC1301B power dissipation is 780 mW, given the following conditions:

Input voltage = 4.2 V

Output voltage of LDO₁ = 2.8 V @ 300 mA

Output voltage of LDO₂ = 1.8 V @ 150 mA

The maximum power dissipated by the device can be calculated by:

P_{D (MAX)} = (V_{IN (MAX)} - V_{OUT (MAX)})/ I_{OUT (MAX)}

Where P_{D (MAX)} is the maximum device power dissipation

V_{IN (MAX)} is the maximum input voltage to the device.

V_{OUT (MAX)} is the maximum output voltage of the device.

I_{OUT (MAX)} is the maximum output current of the device.

The power dissipation of the device is equal to:

P_{D LDO1 (MAX)} = (V_{IN (MAX)} - V_{OUT-LDO1 (MAX)})×I_{OUT-LDO1 (MAX)}

P_{D LDO1 (MAX)} = (4.2 V-2.8 V)×300 mA

P_{D LDO1 (MAX)} = 0.42 W

P_{D LDO2 (MAX)} = (V_{IN (MAX)}-V_{OUT-LDO2 (MAX)})×I_{OUT-LDO2 (MAX)}

P_{D LDO2 (MAX)} = (4.2V-1.8 V)×150 mA

P_{D LDO2 (MAX)} = 0.36 W

P_{D TOTAL (MAX)} = P_{D LDO1 (MAX)}+P_{D LDO2 (MAX)}

P_{D TOTAL (MAX)} = 0.78 W

The thermal resistance junction-to-ambient (R_θJA) of the DFN package is 41°C/W. This DFN thermal resistance specification is based on the 4-layer test method described in the EIA/JEDEC ^[3] JESD51-5 and JESD51-7 standards. In the JESD51 specification, some of the conditions that the test calls out are a 4-layer board, with copper thickness of 2 oz on the outer layers, and 1 oz on the inner layers. They also specify two vias be connected to the exposed bottom pad of the DFN package. These vias also are connected to the ground plane.

These details are mentioned because many application boards don't have the 4-layers. Additionally, the copper weight of many boards is 0.5 oz instead of the 1 oz and 2 oz called out by EIA/JEDEC. These differences will produce results that are different as compared to those specified by EIA/JEDEC. Furthermore, these EIA/JEDEC conditions are different than the standard EIA/JEDEC conditions that are called out for packages other than the DFN package.

The model in Fig. 3 can be used to do first-order thermal calculations. This model is put in the simple terms of an electrical system, where power is illustrated as a current source, temperature is referenced as a voltage and thermal resistance is illustrated as a resistance. The definitions of the variables in this model are:

I_SOURCE = Power in Watts

T_J = Chip junction temperature in °C

T_C = Device case temperature in °C

T_A = Ambient temperature in °C

R_θJC = Thermal resistance from chip junction to device case in °C/W

R_θCS = Thermal resistance from device case to copper ground plane (PC board) in °C/W

R_θSA = Thermal resistance from device copper-ground plane to ambient (air) in °C/W

Given the above specifications, the rise in temperature at the junction above ambient of the TC1301B is:

T_J(RISE) = P_TOTAL * R_θJA

T_J(RISE) = 780 mW * 41°C/W

T_J(RISE) = 32°C

The thermal resistance from junction to ambient with a 2-layer board with vias to the copper ground plane that have been poorly placed can be as high as 150°C/W. With this type of layout, the capacitors are connected using vias to the copper ground plane without consideration to thermal issues. With these conditions, the rise in junction temperature is:

T_J(RISE) = P_TOTAL * R_θJA

T_J(RISE) = 780 mW * 150°C/W

T_J(RISE) = 117°C

If this simple 2-layer layout were used in an ambient environment of 25°C, the junction temperature would be equal to:

T_J = T_J(RISE) + T_A

T_J = 117°C + 25°C

T_J = 142°C

This exceeds the specification limit of 125°C continuous operating junction temperature of the TC1301 dual LDO. This overtemperature violation is before any temperature excursions are applied to the application circuit. It appears as if this type of circuit is only good for temperatures below 25°C. If the ambient temperature is 50°C, under a full-load condition, this circuit will produce a junction temperature of 167°C. This junction temperature exceeds the 125°C continuous operating junction temperature called out in the TC1301B data sheet. It's even higher than the maximum operating junction temperature, which is 150°C.

A feasible 2-layer layout for the TC1301B is shown in Fig. 4, with the circuit diagram of this layout shown in Fig. 5. The board construction is a 0.0625-in. FR4 substrate with 1-oz copper traces. The traces reside on the top layer (as shown in Fig. 4) and the copper ground plane is on the bottom. The copper plane is accessed through vias that are identified in Fig. 4 with “Xs.” The vias that are pointed out in Fig. 4 are placed as close as they can be to the DFN device. The required 0.1 µF ceramic capacitors are attached as close as possible to the output pins of both LDOs. Using this board design results in a junction-to-ambient thermal resistance (R_θJA) of 78°C/W.

With this new thermal resistance, the rise in junction temperature is:

T_J(RISE) = P_TOTAL * R_θJA

T_J(RISE) = 780 mW * 78°C/W

T_J(RISE) = 61°C

The rise in temperature for the layout shown in Fig. 4, under full-load conditions of the TC1301B, is increased from a T_J(RISE) of 32°C (4-layer with vias, EIA/JEDEC standards) to a T_J(RISE) of 61°C (improved 2-layer board). This is certainly an improvement from the first 2-layer board, which had a T_J(RISE) of 117°C. The change in this delta temperature from the EIA/JEDEC specification to the improved 2-layer board performance is primarily the result of a lack of internal layers and vias directly into the copper plane, as defined by the EIA/JEDEC standard.

In conclusion, new power-management devices are available that decrease the cost and increase the performance of application circuits. These devices are for applications that require more than one output voltage. To squeeze the total capability available out of these packaged parts, an understanding of the thermal management and performance issues is essential.

References

“Dual LDO with Microcontroller RESET Function,” TC1301A/B, Microchip Technology Inc., DS21798.
Terry Cleveland, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application,” Microchip Technology Inc., AN792.
EIA/JEDEC Standards JESD 51-5, 51-7.
“TC1301/TC1302 Evaluation Board User's Guide,” Microchip Technology Inc., DS51427.
Terry Cleveland, “Testing the Junction Temperature of Small Outline Packaged Devices,” Dec. 17, 2003, WebSeminar, www.microchip.com.
“Low Quiescent Current Dual-Output LDO,” TC1302A/B, Microchip Technology Inc., DS21333.
“MLP Application Note: Comprehensive User's Guide (MLP, Micro Leadframe Package),” Carsem, April 2002.