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Testing High di/dt Converters

Sept. 1, 2004
There is an increasing demand for point-of-load (POL) converters that maintain good regulation in the presence of fast load transients (di/dt). For example,

There is an increasing demand for point-of-load (POL) converters that maintain good regulation in the presence of fast load transients (di/dt). For example, Artesyn recently introduced POL converters capable of handling transients up to 300 A/µs. This level of performance presents new challenges to engineers during the converter design, and also during the test and verification stages of product development.

The combination of high-frequency (1-MHz) converter operation and fast load transients demands stringent design practices and a thorough understanding of every element of the design and test setup. This article looks at some of the challenges and issues posed during such a design and discusses issues relating to the reliable testing of such a design.

The Need for Higher di/dt

Faster semiconductors not only require more current and lower voltages, but also give rise to higher rates of change of current during operation. As a result of the increase in complexity of integrated circuits according to Moore's Law, all modern devices require a low voltage with high instantaneous current power source.

High di/dts now mean vendors require a fast converter that maintains good load regulation in the presence of a transient. When producing a power-supply solution to cater for this requirement, the converter design is only the first step. You must then verify the performance of the design. With di/dt requirements reaching 300 A/µs and beyond, this is no longer a trivial task.

Load regulation can be defined as the ability of the power supply to control the output voltage level as the load on the power supply increases or decreases. We can then define transient response as a measurement of how quickly and effectively the power supply can adjust to these sudden changes. A switching power supply uses a closed feedback loop to allow measurements of the output of the supply to control the way the supply is operating.

As mentioned in the description of load regulation, the output voltage of a signal varies as the load on it varies. In particular, when the load is changed, the voltage level will shift. If the output voltage is under heavy load from a demanding component and it suddenly stops drawing current, the voltage may temporarily surge if the converter cannot sink the required current. This is called a voltage overshoot. Conversely, if the load demand suddenly increases and the converter cannot source the required current, the voltage level may decrease, which is referred to as voltage undershoot. Fig. 1 shows the undershoot and overshoot (Channel 1) as the load demand is increased and decreased (Channel 3).

The power supply must respond to these sudden changes with minimal transient voltage deviation and recovery time. The deviation and speed of recovery is fully quantifiable, and a power supply can be specifically designed to minimize both of these effects.

Designing for Fast Response Times

While the detail of fast transient response design is outside the scope of this article, it's worth summarizing what is involved. Any increase in load on the output is initially drawn from the output capacitor before the control loop has time to recover and adjust accordingly, as shown in Fig. 2. So, very quickly we have some general design requirements:

  • Higher switching frequencies
  • Smaller inductances
  • Increased capacitance
  • Reduced ESR of output capacitors.

To combine all of the above in the most effective fashion requires power-supply design experience, analog circuit design and analysis, magnetic component design, and innovative design. These requirements are much like those of any design project. The new variable now introduced is the difficulty in testing the final design given the higher di/dts involved.

Limitation of Standard Electronic and Bench Test Equipment

The need to simulate low voltage, high current with fast di/dt loading has become more important than ever. In the past, an electronic load would have been sufficient for test requirements. Di/dt capabilities of up to about 10 A/µs can be achieved in most low- to medium-cost electronic loads. However, as the requirement for faster-load-step generation increases, we are now faced with the dilemma of paying for electronic loads that are targeted at the voltage regulator module (VRM) market.

The leading-edge load in this market segment will deliver 1000 A/µs, and will allow one to qualify all main board Intel microprocessor power performance requirements. This kind of product may be overkill for the nonisolated POL requirements, and means paying for a feature-set that will never be fully utilized. Even if the electronic loads are capable of high slew rates, the distribution associated with cables and the standard interface represents unacceptable inductive losses.

A cost-effective method for generating fast di/dts is to implement an embedded solution on a test card. The circuit diagram shown in Fig. 3 is essentially a 555 timer with driver, turning on and off a series of FETs. The turn on/off slew rate is programmable via two series trim pot resistors. Ideally, the implementation of this circuit on a PCB should take into account the placement/connection of the unit under test, as this will reduce dramatically any parasitic inductance that might otherwise occur in flying leads and so on.

To approximate the rise or fall time of the transient circuit, we can use the formula:

where Vout is the output setpoint, RL is the parallel combination of R8, R9, R11, and R12 on the evaluation board, Rise_time is the rise time of the load (shown as Channel 1 in Fig. 4), and Fall_time is the fall time when the module is sinking current.

In the example shown in Fig. 4, the output voltage was 3.3 V, RL = 0.5 Ω and rise time = 600 ns (measured from a scope). So, the calculated di/dt was 11 A/µs. We see from Channel 4 on the scope above that the deviation was 43.1 mV, and recovery time was approximately 4 µs. R14 and R15 can be varied to independently set the rise time and fall time between minimum and maximum di/dts as per your unique requirements.

However, sometimes step load testing doesn't reveal the stability of the loop at all, particularly when the loop is fast and the rise time of the step is slow. A common method of determining transient response is to do step load testing. Unfortunately, step load testing doesn't tell the whole story. It doesn't reveal conditionally stable loops, and so must be tempered with phase margin. Phase margin is a critical figure of merit, which serves to indicate the stability of a closed loop control system.

Understanding Phase Margin and Bode Plots

Phase margin is one of the most common design verification measurements made in power systems. It is the phase difference between the input and output of an open-circuit control loop at a frequency where the loop has unity gain.

A Bode plot (plot of log gain versus log frequency and linear phase versus log frequency) gives all the information necessary to evaluate a loop. Gain and phase margins are taken directly from the plot. Transient response time is proportional to the loop bandwidth and the amount of ringing is predictable from the measured phase margin.

Fig. 5 shows a sample Bode plot. A phase margin of 72 degrees gives no ringing or overshoot. A phase margin of 60 degrees results in one overshoot but no undershoot or ringing. A phase margin of 45 degrees gives a few cycles of ringing but has a short settling time.

The total voltage excursion from a step load can be calculated by the formula:

ΔV = ΔI / (C × F)

where ΔV is the peak voltage excursion (V), ΔI is the step load current (A), C is the output filter capacitance expressed in Farads, and F is the bandwidth of the voltage feedback loop (Hz). The time to recover is given by:

T = 1 / 4 × f × Cos (Φ m)

where T is the recovery time in seconds, f is again the bandwidth of voltage feedback loop (Hz) and Φ m = phase margin of voltage feedback loop in degrees.

What Are We Trying to Measure?

What we are attempting to measure accurately is the reaction of the unit to a load step. In conjunction with this, we also need to establish the load step demand that the unit sees. Fig. 6 shows the block diagram of the load-step applied to a buck topology dc-dc converter design. In the closing section, we'll talk briefly about what measurement errors can be introduced. Here we talk about what the user should expect to measure.

When a dynamic load demand is placed on a unit, we would ideally have iL (current in the inductor) change instantaneously. However, this isn't possible, because this would require our inductance value to be zero. Also, we have the situation where the ESR of the output capacitor will determine the rate at which current can be supplied from this source. Again, while this can be reduced during the design stage, it can never be eliminated.

Furthermore, the control loop can't react instantly, and when it eventually does react, the rate of recovery will be determined by the response time of the control loop. This means the output voltage will drop off (but recover at a later time). The resultant current flowing in each component is shown in Fig. 7, which also shows the change in output voltage.

Fig. 7 shows the output current demand (io) during a load step along with the resultant current in the output capacitor (ic), the average current in the output inductor (iL ave) and the resultant output voltage (ΔVout). When a load is step is applied at t1, the capacitor supplies the current until the control loop is able to supply the current. A drop in the output voltage is a function of the ESL.

Between t2 and t3, the capacitor is discharged until time t3 when the output average current in the choke is equal to the current demand. From t4 to t5, we have the capacitor charged. Yet the inductor cannot change instantaneously and the resultant charge causes an excess charge on the output capacitor, which results in some overshoot on the output. The period t6 to t8 is a function of the control loop and will be characterized by the phase margin.

Effect of Stray Inductances

Faraday's law states that V = L × di/dt. Now that we are dealing with higher di/dt rates, it means even a stray inductance of several nanohenries can be significant. Not only do we need to consider the parasitic inductance in the PCB tracks that could limit the rate of change of current, but we also need to ensure that what we are measuring is what the unit under test is experiencing. Even the grounding of scope probes can introduce some parasitic inductive loops that can give false readings and must be considered when taking scope measurements.

Typical parasitic values associated with FR4 PCB materials and design.*Description Inductance Resistance Comments Plane to plane 20nH/m 80mV/m Track to plane 30nH/m 500mV/m Track to track 150nH/m 750mV/m Different sides Track to track 600nH/m 1000mV/m On same side µ Via 20pH Via 15pH *Note: Approximations assume 1-mm wide tracks and 9-mm wide planes.

To reduce the deviation due to a load transient, the capacitance is most critical. Placing extra capacitance at the load can reduce the effect on transient response. But take caution when selecting the type of capacitor, which should ideally be a multilayer ceramic chip-type. ESL and ESR will have the same effect whether these capacitors are placed on the module or at the load. The placement of these capacitors should be in a fashion that minimizes the parasitic inductance effect on the layout. The table indicates the level of parasitics that can be inherent in a PCB layout.

High-Frequency Measurement Techniques

A number of issues can lead to measurement errors, including noise pickup, common-mode currents, impedance mismatches, bandwidth issues and scope grounding. Di/dt activity creates induced voltages and currents in parasitic inductances. Devices are coupled to ground either directly by a dc path or by capacitance, and these induced currents can propagate out into the system. The amount of current on any interface will be related to the impedance of the path to ground.

Because of the high level of switching activity in and around the converter, radiated fields may create problems when taking measurements. Loop antennas are especially effective at picking up radiated noise, and the probe and ground lead form a very nice loop with an approximate area of 40 cm2.

Radiated pickup can be minimized by getting rid of the ground lead, clip and scope probe and replacing them with a 50-Ω sub-miniature PCB connector with a suitable coupling system. This reduced loop area will lessen the amount of radiated pickup. Most connector manufacturers will recommend an upper bandwidth limitation when taking measurements. This is done to eliminate very high frequency ringing and noise spikes.

The adoption of techniques similar to those in this article during design and production test has helped Artesyn characterize and introduce dc-dc converters offering new levels of performance to the electronic OEM market.

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