Managing Board Design For LGA Power Converters

May 1, 2005
As some of the newer dc-dc point-of-load (POL) converters are packaged into smaller and smaller surface-mount packages, thermal and electrical layout

As some of the newer dc-dc point-of-load (POL) converters are packaged into smaller and smaller surface-mount packages, thermal and electrical layout is becoming critical. One of the packages that meets many of these requirements is the land grid array (LGA) package. This package is designed to meet the demanding electrical and thermal requirements for minimum footprint POL devices used in the intermediate bus architecture (IBA).

The small size of the LGA dictates that most of the thermal dissipation be conducted through the motherboard, so that efficient thermal design is paramount to its successful operation. In addition, critical electrical paths require low parasitic impedances on the motherboard to maintain circuit performance. The X3015P 15-A LGA dc-dc converter from Power-One (Camarillo, Calif.) is used as an example to illustrate some of the board layout techniques and the thermal calculations needed to ensure proper operation of the converter.

A typical LGA dc-dc converter package usually incorporates several semiconductor die whose overall power dissipations depend on individual device operating conditions. The dc-dc converter junction temperature (TJ) is usually specified for all the components in the package. However, to assure that the maximum junction temperature is not exceeded for all the components, calculations need to be done for the die with the highest temperature.

Since most of the power is dissipated by the switching FET die, which are not usually located in the center of the device, it can be safe to define a package temperature TC at the position that is above the FETs. All measured and modeled package temperatures for the X3015P are referenced to this location, as shown in Fig. 1. Ensuring that the temperature at this location does not exceed the recommended maximum will ensure that all components of the LGA package remain within their respective safe operating limits.

In any application involving power handling, it is important to assure that the silicon junction temperature is not exceeded. Given a measurement of case temperature (TC), the junction temperature (TJ) may be determined from the power dissipation (Q) and the appropriate value of junction-to-package thermal resistance (ΘJT):

TJ = TC + (Q × ΘJT)

For example, consider an application using the X3015P with VIN=5 V, VOUT=1.3 V and a load current of 12 A. Ambient air temperature is 55°C and airflow is 200 LFM. In this instance, the measured case temperature is 67°C, the power dissipation is 2 W and ΘJT=3.9°C/W, giving:

TJ = 67°C + (2 × 3.9)°C=75°C

The majority of heat generated by the LGA is dissipated through the exposed pads to the motherboard. Consequently, the motherboard configuration is important in achieving good thermal performance. It is recommended that the motherboard operating temperature in the immediate vicinity of the POL converter should not be higher than 90°C for reliable operation. The LGA package contains large pads to provide low thermal and electrical impedance connections to the motherboard. The corresponding motherboard pads need to provide efficient electrical and thermal paths.

A high-current dc-dc converter operates at high frequency and, therefore, the layout is critical in achieving optimum performance. Both the input and output filters should be placed as close as possible to the converter. Input noise is minimized by placing the input filter capacitors adjacent to the device, to suppress any noise generated from the parasitic inductance of long trace paths to the device.

Since the output current limit relies on sensing the output inductor current across both the inductor ESR and trace resistance to the point of load, it is critical that the impedance of this trace is minimized by making it as short and wide as possible.

Thermal vias are essential for the reliable operation of the LGA-packaged converter. The number and placement of vias will depend on the application and the thermal properties of the motherboard. Increasing the via density will decrease the thermal resistance; however, there is a diminishing return and a point beyond which adding further vias is of little benefit.

It is important to plug or tent the vias directly under the LGA device with solder mask to prevent any solder wicking inside the vias during reflow, as shown in Fig. 2. Note that the surface area of the LGA pad around the vias must be kept free from solder mask.

The example in Fig. 2a shows a standard via with an exposed land. This type of via is not to be used under the pads of the LGA. The exposed land allows solder to be wicked down a via during reflow and will result in insufficient solder being available to form a reliable solder joint. Fig. 2b depicts a standard via with a tented land. The solder mask should be tented from the topside of the via, thus preventing solder from wicking down the via. And finally, Fig. 2c illustrates a standard via filled with solder mask. This is the most effective way to prevent solder wicking down a via.

Voids in the solder joint, generated during the manufacturing process, may increase the thermal impedance. The effect is not significant for moderate void volumes and a limit of less than 25% on an LGA is acceptable in accordance with the IPC-A-610 standard. However, it is recommended that any voiding on the main power train be limited to less than 15% for optimum thermal results.

Of the two types of land patterns that are used for surface-mount packages — nonsolder mask defined pads (NSMDs) and solder mask defined pads (SMDs) — NSMDs are the approach recommended for the LGA (Fig. 3). The NSMD patterns offer several advantages including tighter control in the copper etch process than the SMD process. A 1-to-1 ratio between the package pad and the pc-board pad for the LGA package is recommended, although ratios down to 0.90 are acceptable.

Note that NSMD pads require a ±0.075-mm clearance around the copper pad and solder mask to avoid overlap between the solder joint and solder mask. For relatively large pads, it is better to split the pad up to prevent skewing and reduce voiding and solderballs.

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