Electronic Design
EDA Tools Got Faster And Easier To Use In 2012

EDA Tools Got Faster And Easier To Use In 2012

joe-d-horizontal_1The march toward faster, smaller, and more powerful products continues. Transistor counts are skyrocketing—and so is the pressure to get to market. Designers need tools that can handle these complexities quickly and reliably. Fortunately, updates of popular products from Cadence and Atrenta as well as a new tool from Ausdia speed up and simplify design.

Cadence’s OrCAD 16.6

OrCAD, the old stalwart of printed-circuit board (PCB) design tools, got a significant upgrade this year. Cadence OrCAD 16.6 sports a bevy of new features, enhanced customization capabilities, and 20% simulation performance improvements, giving users a shorter, more predictable path to product creation (Fig. 1). Additionally, the package has a new signal-integrity flow for greater usability and productivity due to a higher level of automation. This is especially true for circuit simulation of performance-driven digital circuits requiring pre-layout topology and constraint exploration and development for high-speed design.

1. Cadence’s OrCAD 16.6 sports a bevy of new features plus a 20% boost in simulation performance.

OrCAD 16.6 PSpice improves user productivity by providing simulation convergence improvements and an average 20% gain in simulation speed. These significant performance gains are achieved through the introduction of multicore support for simulations involving large designs and designs dominated by complex models such as MOSFETs and bipolar junction transistors (BJTs).

The expanded signal-integrity flow in release 16.6 provides a seamless, bidirectional interface between OrCAD Capture and OrCAD PCB SI. This new integration streamlines pre-layout topology and constraint exploration via an automated and comprehensive design methodology, improving productivity significantly.

“Engineers will gain significant usability, performance, and productivity improvements by leveraging the new capabilities available in the OrCAD 16.6 product line,” said Josh Moore, director of product marketing for OrCAD, System and Software Realization Group, Cadence. “This release of the OrCAD products evolves and advances the Cadence mainstream PCB design solutions, so customers are better equipped to address today’s challenges in high-speed and mixed-signal design.”

OrCAD 16.6 also extends the Tcl (Tool Command Language) programming capability and apps methodology from OrCAD Capture to PSpice. As a result, users can extend and customize their simulations and environment beyond what is possible with a standard “out-of-box” solution. With Tcl access to the simulation data and environment, users may customize simulations with tolerances on any parameter, map user parameters, or program PSpice with user-defined equations and expressions.

Atrenta SpyGlass V4.7

A perennial favorite among users, version 4.7 of Atrenta’s SpyGlass offers significant improvements in speed, usability, and analysis capabilities. This latest release delivers automated register transfer level (RTL) power reduction that is, on average, twice as effective across a broad range of designs compared to previous releases. Run-time and memory usage have also been enhanced in 4.7. For example, customers have reported running 280 million gate designs flat through SpyGlass in four hours.

Many of the analysis features of SpyGlass have also been improved. UPF 2.0 support has been extended in SpyGlass Power Verify. A unique power intent-aware change data capture (CDC) analysis enables early verification of CDC issues around isolation logic at RTL. Glitch detection reporting has been enhanced. And, SpyGlass DFT DSM now provides more comprehensive at-speed testability analysis. SpyGlass Constraints analysis now enables designers to consolidate Synopsys design constraints (SDCs) associated with different modes into a single SDC through an SDC mode merge capability.

An improved user interface for SpyGlass Physical enables designers to quickly analyze and pinpoint logical congestion issues within their RTL. Also included, a unique design complexity analysis based on cyclomatic metrics adds to SpyGlass Advanced Lint. The Atrenta Console graphical user interface provides several usability enhancements for netlist and schematic viewing as well.

“The SpyGlass platform is helping our customers produce higher quality RTL, resulting in faster time to market and improved IP reuse,” said Mike Gianfagna, vice president of marketing at Atrenta. “The 4.7 release of the platform contains many enhancements and several new features that respond directly to our customer’s requests. I am confident the new version will see wide deployment.”

Synopsys HAPS-70 Series

The Synopsys HAPS-70 series FPGA-based prototyping systems improve performance by a factor of three while increasing prototyping capacity to 144 million ASIC gates. Synopsys extended its HAPS product line to address the increasing size and complexity of system-on-chip (SoC) designs. The HAPS-70 systems have tightly integrated prototyping software and hardware, including high-speed time-domain multiplexing (HSTDM) technology (Fig. 2). In combination with new Haps Trak 3 I/O connectors, these features deliver up to three times the prototype performance over traditional connector and pin multiplexing technology.

2. The Synopsys HAPS-70 series software/hardware FPGA-based prototyping system improves performance by a factor of three over its previous version while increasing prototyping capacity to 144 million ASIC gates.

The new prototyping systems also take advantage of a scalable architecture and the latest generation Xilinx Virtex-7 FPGAs. The system supports a wide range of design sizes with capacities from 12 million to 144 million ASIC gates. The flexibility and matched pin connections between the Virtex-7’s I/O banks and Haps Trak 3 connectors enable HAPS users to utilize I/O bandwidth where it’s needed most while minimizing the number of unused pins.

“The stacked silicon interconnect technology of the Virtex-7 2000T FPGA delivers 2 million logic cells of capacity and 12.5-Gbit/s serial transceivers, making it ideal for ASIC prototypes that require both high capacity and high-speed I/O,” said Tim Erjavec, vice president of FPGA platform marketing at Xilinx. “The Synopsys HAPS-70 series takes advantage of the Virtex-7 2000T FPGA’s increased design capacity and I/O bank organization to deliver a system that eases design planning within and across multiple FPGAs while allowing the HAPS-70 to scale up to support multimillion-gate ASIC SoC designs.”

HAPS-70 systems are integrated with an intelligent prototyping software environment for faster partitioning. Additionally, automation of the creation and debug of prototypes for a range of designs from individual IP blocks and processor subsystems to complete SoCs eases the path from RTL to operational prototype. The modular architecture of the HAPS-70 systems gives engineers a common prototyping environment for IP and SoC software development, hardware/software integration, and system validation, reducing duplication of effort across projects.

New “HAPS-aware” features of Synopsys’ Certify multi-FPGA prototyping software increase prototyping productivity by up to 10 times with patent-pending algorithms to automate logic partitioning and live hardware queries to ease system bring-up compared to manual partitioning methods. The new prototyping systems also support HAPS Deep Trace Debug for greater debugging efficiency, providing approximately 100 times more signal storage capacity than the traditional memory storage employed by on-chip FPGA logic debuggers.

For easier system validation and software development, DesignWare Interface IP such as USB 3.0, PCI Express, and HDMI are validated on HAPS systems. With pre-validated DesignWare IP on HAPS systems and a rich selection of daughter cards for common IP protocols, designers can start software development earlier in the product development cycle and reduce IP integration effort. 

Synopsys’ Universal Multi-Resource Bus (UMRBus) host connectivity option for the HAPS-70 system has been enhanced to support up to 400-Mbyte/s bandwidth. The UMRBus provides a seamless link between HAPS-70 systems and Synopsys’ Virtualizer-based virtual prototypes to create an integrated hybrid prototyping environment for early software development and hardware/software integration. The UMRBus also provides remote access, a generic C++/TCL programming interface, and co-simulation with Synopsys’ VCS functional verification solution along with hierarchical block level bring-up and debug, enabling the HAPS-70 system to be incorporated into the design flow earlier.

“Increasing design size, software complexity, and the earliest possible software development are key challenges for SoC prototypers,” said John Koeter, vice president of marketing for IP and systems at Synopsys. “The extended capabilities of the HAPS-70 system further shorten software development and hardware/software integration by delivering industry-leading FPGA-based prototyping capacity and performance with intelligent partitioning and debugging tools. By leveraging our technology leadership spanning hardware, software, and IP, designers are immediately productive with validating their largest chip designs.”

The HAPS-70 FPGA-based prototyping systems are available now to early adopters in nine model variants, with capacities from 12 million to 144 million ASIC gates.

Ausdia Timevision

Ausdia is a new company in the EDA space, making its debut at this year’s Design Automation Conference. Sam Appleton founded the company with another engineer literally in a garage back in 2006. Despite the company’s youth, though, its Timevision solution for timing constraints development and verification will have an impact on the industry. It suits team members at the RTL, STA/synthesis, and implementation stages.

Appleton calls Timevision a next-generation tool that takes full advantage of modern multicore computers. It supports designs up to 200M instances. Constraint verification, even on a large design, is typically less than one hour. For example, a 5M-instance, 120-clock design runtime on a four-core server is around 45 minutes. Also, Timevision runtimes are five to 10 times faster than STA tools for constraint checking, according to the company.
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